Digital data transfer apparatus and method

Cryptography – Communication system using cryptography – Pseudo-random sequence scrambling

Reexamination Certificate

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Details

C710S104000, C710S107000, C710S120000, C710S108000

Reexamination Certificate

active

06496583

ABSTRACT:

TECHNICAL FIELD
This invention relates to a method and apparatus for transmitting digital data.
BACKGROUND ART
As an interfacing standard supporting high-speed data transfer and real-time transfer, with a view to interfacing for data transfer, there is known the IEEE 1394 high-Performance Serial Bus Standard (IEEE 1394 standard).
This IEEE 1394 standard provides data transfer speeds at 100 Mbps (98.304 Mbps), 200 Mbps (196.608 Mbps) and 400 Mbps (393.216 Mbps). The 1394 port, having an upper order transfer speed, is prescribed to maintain compatibility with respect to its lower order transfer speed. Thus, the data transfer speeds of 100 Mbps, 200 Mbps and 400 Mbps can co-exist on the same network. Also, in the IEEE 1394 standard, a transfer format of the DS-LINK (DATA/STROBE LINK) encoding system is used, in which transfer data are converted into data signals and strobe signals supplementing the data signals, as shown in
FIG. 1
, and in which clock signals are generated by taking an exclusive OR of the two signals. Referring to the cable structure shown in a cross-sectional view of
FIG. 2
, there is prescribed a cable
200
of a structure in which a cable obtained on bundling two sets of twist pair lines (signal lines)
202
shielded by first shield layers
201
and power source lines
203
is further shielded by a second shield layer
204
.
In the connection system of the IEEE 1394 standard, two types of systems, namely a daisy chain system and a node branched system, may be used. With the daisy chain system, up to a maximum of 16 nodes (an equipment having the 1394 port) can be connected, with the maximum length between the nodes being 4.5 m. By using node branching in combination, as shown in
FIG. 3
, it is possible to connect up to 63 nodes possible with the standard (physical node addresses).
With the IEEE 1394 standard, connection or disconnection of the above-described cable can be performed with the equipment remaining in operation, that is in the power up state, so that the 1394 network can be re-constructed automatically at a time point of node addition or deletion. The equipment of the node connected at this time can be recognized automatically. The ID or layout of the connected equipments can be managed on the interface.
The constituent elements of the interface conforming to the IEEE 1394 standard as well as the protocol architecture are shown in FIG.
4
. The interface of the IEEE 1394 can be classified into the hardware and the firmware.
The hardware is made up of a physical layer (PHY) and a linked layer (link layer).
In the physical layer, signals of the IEEE 1394 standard are driven directly. The link layer has the host interface and the physical layer.
The firmware includes a transaction layer, made up of a management driver for performing actual operations for the interface conforming to the IEEE 1394 standard, and a management layer, made up of a driver for network management conforming to the IEEE 1394 standard, termed Serial Bus management (SBM).
The application layer includes a software used by the user and a management software for interfacing the management layer or the transaction layer.
In the IEEE 1394 standard, the operation of transfer performed in the network is termed a sub-action, for which the following two sorts of the sub-action are prescribed. That is, as the two sub-actions, an asynchronous transmission mode, termed “asynchronous”, and a synchronous transfer mode guaranteeing a transfer area, termed “isochronous”, are defined. Each sub-action is divided into three parts, and assumes the transfer states termed “arbitration”,“packet transmission” and “acknowledgment”.
In the asynchronous sub-action, asynchronous transfer is used. In
FIG. 5
, showing the temporal transition state in the transfer mode, the first sub-action gap specifies the idle state of the bus. By monitoring the sub-action gap time, the directly previous transfer comes to a close and judgment is given as to whether or not new transfer is possible.
If the idle state continues for longer than a preset time duration, a decision is given that a node desiring the transfer can use a bus, and arbitration is executed in order to acquire a bus control right. A decision to stop a bus actually is given by a node B positioned at a root, as shown in
FIGS. 6
a
and
6
b
. The node which has acquired the bus control right by this arbitration then executes data transfer, that is packet transmission. After the data transfer, a node which has received data returns a code ack (code returned to acknowledge the reception) responsive to the received result for the transferred data to execute response acknowledgement. By executing this acknowledgement, both the transmission and receiving nodes can confirm by the ack contents that transfer has been completed regularly.
The sub-action gap, that is the bus idle state, is then resumed to repeat the above transfer operation.
In the isochronous sub-action, transfer of a structure basically similar to the asynchronous transfer is executed. This transfer is executed in preference to the asynchronous transfer in the asynchronous sub-action, as shown in FIG.
7
. This isochronous transfer in the isochronous sub-action is executed in preference to asynchronous transfer in the asynchronous sub-action approximately every 8 kHz to set a transfer mode which guarantees a transfer area. This realizes transfer of real-time data.
If isochronous transfer of real-time data is to be executed simultaneously in plural nodes, a channel ID for distinguishing the contents (transmission node) is set in the transfer data in order to receive only the required real-time data.
The physical layer in the above-described IEEE 1394 standard is made up of a physical layer logical block (PHY LOGIC)
102
, a selector block (RXCLOCK/DATA SELECTOR)
103
, port logic blocks (PORT LOGIC
1
, PORT LOGIC
2
, PORT LOGIC
3
),
104
,
105
,
106
, cable ports (CABLE PORT
1
, CABLE PORT
2
, CABLE PORT
3
)
107
,
108
,
109
and a clock generating block (PLL)
110
, as shown in FIG.
8
.
The physical layer logical block
102
performs I/O control and arbitration control with the link layer in the IEEE 1394 standard and is connected not only to a link layer controller
100
but also to the selector block
103
and to the port logic ports
104
,
105
,
106
.
The selector block
103
selects data (DATA
1
, DATA
2
, DATA
3
) received via logical blocks
104
,
105
,
106
, connected to the cable ports
107
,
108
,
109
, and reception clocks (RXCLK
1
, RXCLK
2
, RXCLK
3
), and is connected to the physical layer logical block
102
and to the port logic ports
104
,
105
,
106
.
For reception, each set of packet data DATA
1
, DATA
2
, DATA
3
received via the port logic ports
104
,
105
,
106
and the reception clocks (RXCLK
1
, RXCLK
2
, RXCLK
3
) is selected to send the received packet data and the reception clocks via cable ports
107
,
108
,
109
to the physical layer logical block
102
. If, for example, the packet data DATA
1
received via the port logical block
104
via cable port
107
and the reception clock RXCLK
1
are selected, the received packet data (DATA
1
) and its reception clock RXCLK
1
are sent by the port logical block
104
to the physical layer logical block
102
. The packet data selected by the selector block
103
is written by the reception clock in a FIFO memory in the physical layer logical block
102
. The packet data written in the FIFO memory is read out by a system clock SYSCLK provided by a clock generating block
110
.
The port logical block
104
sends/receives an arbitration signal (ARB.SIGNAL) and data (DATA
1
) via cable port
107
and has the function of generating reception clocks (RXCLK
1
) from the data signals sent via cable port
107
and its strobe signals. This port logical block
104
is fed during arbitration with an arbitration signal (ARB. SIGNAL) from the physical layer logical block
102
.
During data transmission time, the port logical block
104
converts the packet data DATA
1
sent via selector block
103

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