Digital data separator

Details Digital data separator Digital data separator

1999-10-28

2003-12-16

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

C375S365000, C375S355000

Reexamination Certificate

active

06665359

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital data separators and more particularly to a digital data separator for recovering digital data stored in a run length limited data stream.
BACKGROUND OF THE INVENTION
Magnetic and optical storage media, such as floppy disks and CD-ROM, store digital data in encoded formats containing both the digital data and clock information. Accordingly, the encoded digital data stream contains clock signals at regularly spaced intervals, “the clock windows,” with binary data signals interspersed between successive clock signals, the “data windows.”
FIG. 1
shows an encoded data stream
100
having a plurality of logic 1's
102
and a plurality of logic 0's
104
. In this example, encoded data stream
100
is encoded using modified frequency modulation (“MFM”) to combine non-return to zero data stream
110
information with write clock stream
120
information. In the particular technique of this example, there exists a minimum of one logic 0
104
and up a maximum three logic 0's
104
between each logic 1
102
in encoded data stream
100
.
As one of ordinary skill in the art recognizes, the spacing of logic 1's
102
and logic 0's
104
provide enough timing information to ensure an accurate signal recovery during a read process even in the presence of timing errors in reading or writing encoded data stream
100
. Basically, timing errors exist due to disk rotational speed errors, magnetic or optical interference, electrical noise, etc. Because of these errors, reading devices need to compensate for timing deviations when extracting the encoded data and clock information.
Early techniques for separating data information from clock information in the encoded data stream used an analog phase-locked loop (“PLL”).
FIG. 2
shows one possible analog PLL system
200
. Analog PLL system
200
included a phase detector
202
, a low-pass filter
204
, and a voltage controlled oscillator (“VCO”)
206
. VCO
206
recovers the clock signals and supplies a recovered clock signal
208
to phase detector
202
. Phase detector
202
compares signal
208
an encoded data stream input
210
to obtain phase detector output
212
. Phase detector output
212
includes a low frequency error portion and a high frequency error portion. The low frequency error portion is due to the phase difference between the signal
208
and input
210
. The high frequency error portion is due to bit jitter. Phase detector output
212
passes through low-pass filter
204
prior to being input into VCO
206
to attenuate the high frequency bit jitter potion. The feedback loop formed by analog PLL system
200
compensated for timing errors in the encoded data stream to ensure accurate data recovery. While accurate and functional, analog PLL system
200
is expensive and cumbersome to implement.
Eventually digital PLL systems evolved to replace analog PLL system
200
.
FIG. 3
shows one possible digital PLL system
300
. Digital PLL system
300
includes a synchronizer
302
, a phase detector
304
, a digital controlled oscillator
306
, a transient response and phase correction state machine
308
, and a frequency tracking and correction state machine
310
. Digital PLL system
300
is more fully described in U.S. Pat. No. 4,808,884 to Hull et al., entitled HIGH ORDER DIGITAL PHASE-LOCKED LOOP SYSTEM, which disclosure is incorporated herein by reference. Essentially, digital PLL system
300
compensated for timing errors in reading the encoded data stream by varying the number of registers per window between a nominal number of sixteen and a “slow” number of seventeen and a “fast” number of fifteen. Thus, the data window could be adjusted for frequency errors of ±6% from the nominal frequency. While providing a substantial improvement over analog PLLs, digital PLLs were still cumbersome.
In order to reduce the bulkiness of the analog and digital PLL systems described above, systems for separating data signals from clock signals without using PLLs were developed.
FIG. 4
shows one possible digital data separator system
400
. Digital data separator system
400
includes an edge detector
402
, state generator
404
, and an incremental counter
406
. Digital data separator
400
is more fully described in U.S. Pat. No. 5,835,542 to Lu, entitled DIGITAL DATA SEPARATOR FOR SEPARATING DATA SIGNALS FROM CLOCK SIGNALS IN AN ENCODED DATA STREAM, which disclosure is incorporated herein by reference. Digital data separator
400
operates by inputting an encoded data stream edge detector
402
. Upon detection of a rising edge, edge detector
402
sends a signal to state generator
404
. Substantially simultaneously with the input, counter
406
begins counting clock pulses and inputs the number of counts to state generator
404
. If state generator
404
receives a rising edge transition from edge detector
402
between predefined counts of counter
406
, then the data information recovered is a logic 1, otherwise the data information for that data window is determined to be a logic 0. At the end of each count window (i.e. one data bit cycle), digital data separator
400
determines whether the data stream was a logic 1 or logic 0 and counter
406
is reset to begin counting for the next count window.
While digital data separator system
400
achieves its goal of reducing bulkiness of the data separator, it is limited in its ability to recognize timing errors, some of which are caused by the insertion of logic 0s in the encoded data stream by the encoding process, for example, the run length limited (“RLL”) encoding process inserts one to three logic 0s between each logic 1. In particular, digital data system
400
determines whether a logic 1 or a logic 0 exists for every count window. For example,
FIG. 5
shows an encoded data stream
500
. Data stream
500
was encoded using a RLL encoding process. The RLL encoding process created sub-patterns
502
,
504
, and
506
in data stream
500
. Sub-pattern
502
is a logic 0 followed by a logic 1. Sub-pattern
504
is two logic 0's followed by a logic 1. Sub-pattern
506
is three logic 0's followed by a logic 1. These sub-patterns in encoded data stream
500
cause predictable timing shifts or errors in the data information that are not accounted for by digital data separator
400
causing timing errors to propagate through the data stream and result in data recovery errors. Thus, a digital data separator that accounts for the predictable patterns and sub-patterns caused by the encoding process, for example RLL process, is desirable.
SUMMARY OF THE INVENTION
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings, or may be learned by practice of the invention The advantages and purpose of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To attain the advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, digital data separators consistent with the present invention separate data signals from clock signals in an encoded data stream using a synchronizer to synchronize the encoded data stream with a system clock of the digital data separator. The digital data separators further include an up-counter to count system clock pulses and combinatorial logic to produce a reset signal to reset the up-counter so that the up-counter counts pulses between valid edge detect signals. The combinatorial logic also determines whether a next edge detect signal is valid based on the count of the up-counter.
A method for digital data separation consistent with the present invention includes receiving an encoded data stream and a system clock signal at a synchronizer. The method further includes generating an edge detect signal based on the received data stream, incrementing a counter for every clock pu

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