Digital data processor with two operation units

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G06F 938, G06F 900

Patent

active

045325898

ABSTRACT:
In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.

REFERENCES:
patent: 4110822 (1978-08-01), Porter et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4251859 (1981-02-01), Momose
patent: 4270181 (1981-05-01), Tanakura et al.
patent: 4305124 (1981-12-01), Marro et al.

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