Excavating
Patent
1985-08-02
1987-03-31
Malzahn, David H.
Excavating
371 9, G06F 1120
Patent
active
046548572
ABSTRACT:
A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.
Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.
The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
REFERENCES:
patent: 3469239 (1969-09-01), Richmond et al.
patent: 3544973 (1970-12-01), Borck et al.
patent: 3548382 (1970-12-01), Lichty et al.
patent: 3560935 (1971-02-01), Beers
patent: 3609704 (1971-09-01), Schurter
patent: 3641505 (1972-02-01), Artz et al.
patent: 3665173 (1972-05-01), Bouricus et al.
patent: 3768074 (1973-10-01), Sharp et al.
patent: 3795901 (1974-03-01), Boehm et al.
patent: 3805039 (1974-04-01), Stifflev
patent: 3820079 (1974-06-01), Bergh et al.
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 3879712 (1975-04-01), Edge et al.
patent: 3893084 (1975-07-01), Kotok et al.
patent: 3895353 (1975-07-01), Dalton
patent: 3991407 (1976-11-01), Jordan, Jr. et al.
patent: 3997896 (1976-12-01), Cassarino, Jr. et al.
patent: 4015243 (1977-03-01), Kurpanek et al.
patent: 4015246 (1977-03-01), Hopkins, Jr. et al.
patent: 4032893 (1977-06-01), Moran
patent: 4096571 (1978-06-01), Vander Mey
patent: 4096572 (1978-06-01), Namimoto
patent: 4150428 (1979-04-01), Inrig et al.
patent: 4159470 (1979-06-01), Strojny et al.
patent: 4177510 (1979-12-01), Appell et al.
patent: 4190821 (1980-02-01), Woodward
patent: 4228496 (1980-10-01), Katzman
patent: 4233682 (1980-11-01), Liebergot et al.
patent: 4245344 (1981-01-01), Richter
patent: 4253147 (1981-02-01), McDougall et al.
patent: 4263649 (1981-04-01), Lapp, Jr.
patent: 4279034 (1981-07-01), Baxter
patent: 4304001 (1981-12-01), Cope
patent: 4310879 (1982-01-01), Pandeya
patent: 4323966 (1982-04-01), Whiteside et al.
patent: 4347563 (1982-08-01), Paredes et al.
patent: 4354267 (1982-10-01), Mori et al.
patent: 4356546 (1982-10-01), Whiteside et al.
patent: 4410983 (1983-10-01), Cope
patent: 4428044 (1984-01-01), Liron
patent: 4438494 (1984-03-01), Budde et al.
patent: 4453215 (1984-06-01), Reid
patent: 4484273 (1984-11-01), Stiffler et al.
Su, "A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures" IEEE Tran on Computers vol. C-29, No. 3, Mar.'80, pp. 254-258.
Katsuki, "Pluribus-An Operational Fault-Tolerant Multiprocessor" Proceedings of the IEEE vol. 66, No. 10, Oct. 1978, pp. 1146-1159.
Takaoka "N-Fail Safe Logical Systems" IEEE Trans. on Computers vol. C-20, No. 5, May 1971, pp. 536-542.
"Standard Specification for S-100 Bus Interface Devices" Computer vol. 12, No. 7, Jul. 1979, pp. 28-52.
Kogge, The Architecture of Pipelined Computers Hemisphere Publishing Corp. 1981, (Table of Contents).
Hamming, "Error Detecting & Error Correcting Codes" The Bell System Tech. J. vol. XXVI, Apr. 1950, No. 2, pp. 147-160.
Losq, "A Highly Efficient Redundancy Scheme: Self-Purging Redundancy" IEEE Trans. on Computers vol. C-25, No. 6, Jun. 1976, pp. 564-578.
Depledge, "Fault Tolerant Microcomputer Systems for Aircraft" Conference on Computer Systems & Technology Brighton, Sussex, England, Mar. 29-31, 1977.
Rennels, "Architecture for Fault-Tolerant Spacecraft Computers," Proceedings IEEE, vol. 66, No. 10, pp. 1255-1268, (1978).
Anderson & Lee, Fault Tolerance, Principles and Practice Prentice-Hall International, New Jersey, 1981, (Table of Contents).
The Bell System Technical Journal, Sep. 1964, pp. 1845-1847, 1872-1877, 1966-1980, 2021-2022.
Electronics, "Computers People Can Count On", Jan. 27, 1983, pp. 93-105.
Gorsline, G. W., Computer Organization Hardware/Software, Prentice-Hall, Inc. 1980, pp. 221-227.
AFIPS Conference Proceedings, vol. 41, Part II, 1972, "C.mmp-A Multi-Mini-Processor", W. A. Wulf & C. G. Bell, pp. 765-777.
Computer Design, "Design Motivations for Multiple Processor Microcomputer Systems", vol. 17, Mar. 1978, pp. 81-89.
Computing Surveys, "Multiprocessor Organization--A Survey", vol. 9, No. 1, Mar. 1977, pp. 103-129.
Mano M., Computer System Architecture, Prentice-Hall, Inc. 1982, pp. 454-473.
Baty Kurt F.
Clemson Daniel M.
Dynneson Ronald E.
Falkoff Daniel M.
Hendrie Gardner C.
Malzahn David H.
Stratus Computer, Inc.
LandOfFree
Digital data processor with high reliability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital data processor with high reliability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital data processor with high reliability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2218140