Digital data processor with fault tolerant peripheral bus commun

Details Digital data processor with fault tolerant peripheral bus commun Digital data processor with fault tolerant peripheral bus commun

1987-07-29

1990-05-15

Chan, Eddie P.

Boots, shoes, and leggings

3642402, 3642710, 3642718, G06F 1300, G06F 1342

Patent

active

049263153

ABSTRACT:
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

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