Digital data processor for multiplying data by a coefficient set

Details Digital data processor for multiplying data by a coefficient set Digital data processor for multiplying data by a coefficient set

1984-09-17

1987-10-20

Malzahn, David H.

Boots, shoes, and leggings

364754, G06F 15336, G06F 15347

Patent

active

047018763

ABSTRACT:
A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array of cells consisting of nearest neighbor connected gated full adders. The cells multiply data bits received from laterally adjacent cells and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array. An adder tree accumulates non-simultaneously computed contributions to individual output terms. The tree incorporates a delay and switches arranged to implement or bypass the delay according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

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patent: 4546445 (1985-10-01), Haugen
Kung, "Why Systolic Architectures?", Computer, Jan. 1982, pp. 37-45.
McCanny et al, "Bit-Level Systolic Array Circuit for Matrix Vector Multiplication", IEE Proceedings, vol. 130, Pt. G, No. 4, Aug. '83, pp. 125-130.
Foster et al, "The Design of Special-Purpose VLSI Chips", Computer, Jan. 1980, pp. 26-40.
Thompson, "Digital Arithmetic Units for a High Data Rate", The Radio and Electronic Engineer, vol. 45, No. 3, Mar. 1975, pp. 116-120.
Hallin et al, "Pipelining of Arithmetic Functions", IEEE Trans. on Computers, Aug. 1972, pp. 880-886.

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