Multiplex communications – Wide area network – Packet switching
Patent
1988-03-16
1989-06-20
Griffin, Robert L.
Multiplex communications
Wide area network
Packet switching
H04J 304
Patent
active
048415243
ABSTRACT:
A digital data multiple conversion system which can be used in a digital data communication network and recover lost clock pulses. The system includes a memory unit storing input data having N bits, a first frequency divider frequency-dividing an input clock having a first frequency at N to output a first frequency-divided signal, a first pulse width expansion circuit connected to receive m frequency divided pulses from the first frequency divider, where m indicates the number of lost pulses of the input clock plus one receiving the input clock, and outputting a first pulse width expanded signal of the input clock having an m+1 pulse width, a circuit outputting a read clock having a second frequency near to the the first frequency and stuffing the read clock, a second frequency divider frequency-dividing the read clock at N to output a second frequency-divided signal, a second pulse width expansion circuit connected to receive n frequency divided pulses from the second frequency divider, where n indicates the number of lost pulses of the read clock plus one, receiving the read clock, and outputting a second width expanded signal of the read clock having an n+1 pulse width; a phase detector outputting a phase detection signal when the phases of both pulse width expanded signals coincide, and a stuffing request circuit outputting a stuffing request signal to the stuffing circuit. The stuffing circuit stuffs the read clock in response to the stuffing request signal.
REFERENCES:
patent: 4353129 (1982-10-01), Nishiwaki
patent: 4759041 (1988-07-01), Anderson et al.
Furukawa Takahiro
Kosugi Toru
Miyaou Hirohisa
Chin Wellington
Fujitsu Limited
Griffin Robert L.
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