Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-01-15
2001-04-17
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C714S795000
Reexamination Certificate
active
06219388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a receiving device used for transmitting digital data in satellite communications, mobile communications, and mobile satellite communications. More particularly, the invention relates to a digital data demodulating device using a viterbi algorithm for determining the transmission data.
2. Description of the Related Art
It is well known that, in a receiving device, a viterbi algorithm is very effective when a channel includes an ISI (Inter-symbol Interference) as a device for deciding the data from a transmitted received signal which has been digitally modulated using methods such as PSK (Phase Shift Keying). A conventional digital data demodulating device is discussed below using an example disclosed in “The Viterbi Algorithm” written by G. D. Forney, Jr. (Proc. IEEE, Vol. 61, No. 3, pp. 268-278, March 1973).
FIG. 18
illustrates a model of a channel having ISI. Transmission data S
61
, which has been modulated in BPSK (Binary Phase Shift Keying), are sequentially input to the shift register
61
, which contains (V−1) stages, where, (V−1) is the number of multi-path wave maximum delay symbols that are contained in the received signal. The transmission data S
61
and the output from the shift register
61
are multiplied by tap coefficients (CIR) C
1
, . . . , C
V
, respectively, where CIR represents the channel impulse response. The resulting products are added in an adder
63
. The output from the adder
63
is added to the noise w
n
in an adder
64
, and the adder
64
outputs a received signal S
62
. The received signal S
62
is expressed by the following formula (1), where received signal S
62
is denoted as I
n
, the transmission signal S
61
as I
n
, and the respective outputs from the shift register
61
as I
n−1′
, I
n−2′
, . . . , I
n−(V−1)
.
r
n
=
∑
v
=
1
V
C
v
I
n
-
(
v
-
1
)
+
w
n
(
1
)
In the channel model having the ISI illustrated in
FIG. 18
, the reception data is determined based not only on current transmission data, but also on past transmission data. Therefore, it is necessary to take the past transmission data into account in deciding the current transmission data.
The past transmission data is stored in the shift register
61
. If the shift register length is (V−1) as illustrated in
FIG. 18
, the past transmission data of (V−1) symbol period is stored in the shift register
61
. The past transmission data is stored in pairs in the shift register, and these pairs are defined as “states”. If the shift register length is 2 (V=3), the following four states are included: state [0, 0], state [0, 1], state [1, 0] and state [1, 1]. In order to simplify the explanation, it is assumed here that the transmission data contain only two numbers, 0 and 1. In this case, the number of the states, N
s
, are expressed by the formula N
s
=2
V−1
.
A trellis diagram illustrates state variation which occurs as time passes.
FIG. 19
is a trellis diagram illustrating the state variation when the shift register length is 2(V=3)s. In this case, the state [0, 0] is denoted as state A, the state [0, 1] as state B, the state [1, 0] as state C and the state [1, 1] as state D. In
FIG. 19
, the states A, B, C and D are illustrated in the vertical direction from the top to the bottom, and the time n−1, n, n+1, n+2, n+3 and n+4 are illustrated in the horizontal direction from the left to the right. A line is drawn from each state (each state is represented as a circle) to two other states at the subsequent time. These lines represent the transition of the states according to time. For instance, two lines are drawn from the state A to the state A and the state C of the subsequent time. The line drawn from the state A to the state A of the subsequent time illustrates a state transition when the input data (current transmission data) is 0. The line drawn from the state A to the state C of the subsequent time illustrates a state transition when the input data is 1.
These lines in the trellis diagram are called “branches”. Here, a state at time n is represented as S., and the branches extending from the time n−1 to the time n are represented as S
n−
1/S
n
. As time proceeds, the states change via branches. The track of a state is defined as a path. In
FIG. 19
, examples of paths are illustrated with bold lines. A path starting at time n−1 and ending at time n+4 is represented as S
n−1
/S
n
/ . . . /S
n+4
. Paths determine how states change, at the same time, determine the transmission data sequence I
n
, I
n+2
, . . . , I
n+4
. Therefore, it is possible to determine the transmission data sequence by determining the path at the receiver's end.
A viterbi algorithm determines a sequence of transmission data using the trellis diagram.
FIG. 20
illustrates a conventional digital data demodulating device using a viterbi algorithm. In
FIG. 20
, a CIR estimating circuit
500
and a viterbi processor
100
receive a signal S
1
. The CIR estimating circuit estimates CIR based on the input signal S
1
, and outputs the estimated CIR S
2
. A replica calculating circuit
200
receives the estimated CIR S
2
and calculates a replica S
3
of the received signal S
1
. The viterbi processor
100
receives the signal S
1
and the replica S
3
, determines the transmission data based on the received signal S
1
and replica S
3
according to the viterbi algorithm, and outputs the decision data S
4
.
The replica calculating circuit
200
calculates the replica S
3
of a received signal S
1
using the CIR S
2
, which has been estimated in the CIR estimating circuit
500
. C
1
, C
2
, . . . , C
V
, which represent CIRs for the respective taps V
1
, V
2
, . . . , V
V
, are represented as B
1
, B
2
, . . . , B
V
, which are the estimated CIR S
2
output from the CIR estimating circuit
500
. As the trellis diagram illustrates, the branch S
n−1
/S
n
, which starts at time n−1 and ends at time n, is determined by pairs of the transmission data S
61
and the past transmission data which are stored in the shift register
61
. That is, assuming that candidate for the transmission data S
61
is J
n
, and candidates for the past transmission data are J
n−1
, J
n−2
, . . . , J
n−(v−1)
, vector (J
n
, J
n−1
, . . . , J
n−(v−1)
) takes 2
V
values from (0, 0, . . . , 0) to (1, 1, . . . , 1). Accordingly, the branches S
n−1
/S
n
have 2
V
ways, which start at time n−1 and end at time n. Accordingly, the replica S
3
has 2
V
values, corresponding to the respective branches illustrated in the trellis diagram. A replica R
n
(k) corresponding to the k-th branch (k=1, 2, . . . , 2
V
) are obtained from the following formula (2).
R
n
(
k
)
=
∑
v
=
1
V
B
v
J
n
-
(
v
-
1
)
(
k
=
1
,
2
,
.
.
.
,
2
v
)
(
2
)
In formula (2), the vector (J
n
, J
n−1
, . . . , J
n′(V−1)
) takes different 2
V
values from (0, 0, . . . , 0) to (1, 1, . . . , 1) corresponding to k.
An example of the viterbi processor
100
is illustrated in FIG.
21
. In
FIG. 21
, the same portions as those shown in
FIG. 20
are represented with the same numbers, and repeated explanations of them are omitted. A branch metric generating circuit
110
obtains a respective branch metric corresponding to the respective branches, which are illustrated in the trellis diagram. An ACS processing circuit
120
performs ACS processes (ACS: Add, Compare and Select) based on the branch metric output from the branch metric generating circuit
110
. A path metric memory
130
stores the total sum of the branch metric contained in the candidate paths in the past transmission data sequence. A path memory
140
stores the candidate paths in the past transmi
Kubo Hiroshi
Murakami Keishi
Tanada Kazuo
Chin Stephen
Fan Chieh M.
Mitsubishi Denki & Kabushiki Kaisha
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