Digital data decompression implemented in a field...

Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes

Reexamination Certificate

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C341S050000

Reexamination Certificate

active

11387052

ABSTRACT:
Operations for decompression of compressed data is performed in parallel and in a pipelined manner to generate addresses into a memory on-the-fly rather than using a large look-up table. The logic circuits for doing so are thus reduced to the point of being able to be formed by suitable programming of a field programmable gate array (FPGA) while achieving substantial increase in processing speed beyond speed increases attributable to increase of clock rates.

REFERENCES:
patent: 5650905 (1997-07-01), Bakhmutsky
patent: 5757295 (1998-05-01), Bakhmutsky
patent: 6157326 (2000-12-01), Van Der Vleuten et al.

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