Digital data concentrator

Details Digital data concentrator Digital data concentrator

1994-12-22

1995-12-26

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370112, H04Q 1104

Patent

active

054793980

ABSTRACT:
First multiplexers have inputs connected to communication channels which carry inbound digital words. The output of each of the first multiplexers is coupled to a control buffer that has its output connected to a data input of a random access memory (RAM) of M columns and N rows. The RAM is capable of concurrently storing a digital word entered on each of its data inputs during each clock cycle. During a clock cycle each control buffer: (a) stores an associated inbound word received from a first multiplexer, (b) transmits the associated inbound word to a respective input of the RAM, or (c) does both (a) and (b). The control buffer operates to cause each column in the RAM to be completely filled with inbound words before another column in the RAM receives any inbound words. The packing of the RAM to avoid empty or "fill" cells makes the reading or withdrawing of information straightforward.

REFERENCES:
patent: 5189668 (1993-02-01), Takatori et al.
patent: 5256958 (1993-10-01), Eng et al.
patent: 5412646 (1995-05-01), Cyr et al.

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