Digital data bus system including arbitration

Details Digital data bus system including arbitration Digital data bus system including arbitration

1997-11-17

2000-02-15

Vu, Huy D.

Multiplex communications

Channel assignment techniques

Carrier sense multiple access

370451, H04L 12413, H04L 12403

Patent

active

060260947

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a data bus system including an improved arbitration scheme for resolving conflicting transmissions from different nodes on the data bus. In digital data bus systems, such as current daisy chain type bus systems, there are two bidirectional signal paths on each data path. More specifically, each data port or node has a bidirectional data line and some form of bidirectional strobe or clock signal line. In such a system, it is possible for two or more nodes to attempt to use the bus simultaneously. In such a situation, such nodes are said to be in contention. Because only one node may use the bus at a time, when two or more nodes are in contention, a decision must be made of which of the nodes is to be allowed to use the bus, a process known as arbitration. Typically, in these systems, the arbitration for control of the bus is initiated by detecting the conflict of the output drivers of the nodes in contention. If two nodes are in contention, the possible states of the bus are:


______________________________________ High if both nodes are driving high Low if both nodes are driving low Middle if one node is high and the other is low. ______________________________________
To detect the state of the bus line, three analog level sensors are required. In addition, some form of processing is required after the arbitration is complete to define the direction of the signal transmission for those nodes on the bus between the winning node to the destination node. Multiple level sensors and subsequent processing add cost and complexity to the system.
FIG. 1 is a block diagram illustrating a typical known daisy chain bus system. In FIG. 1, a network of five nodes, A, B, C, D, and E, are connected in a daisy chain bus for interchange of data. Each of the nodes has two connection points, a first connecting to the node on its left (if there is one) and a second connecting to the node on its right (if there is one). In the illustrated embodiment, each connection point contains two signal lines (and possibly more). A first signal line carries bidirectional serial data, and a second signal line carries a bidirectional strobe or clock signal in synchronism with the serial data. The clock signal line is illustrated as the top-most signal line, and the data signal line is illustrated as the bottom-most signal line in FIG. 1. In a daisy chain data bus as illustrated in FIG. 1, the data and clock signal lines are generally bidirectional and the direction of the clock and data signal lines is switched together. That is, the data and strobe lines always transmit data in the same direction.
FIG. 2 is a more detailed block diagram of a prior art node (A; B, C, D or E) in the network illustrated in FIG. 1. In FIG. 2, a left hand connection point 5L includes a clock signal line 7L and a data signal line 9L. The clock signal line 7L and data signal line 9L are coupled to an adjacent node (not shown). The clock signal line 7L and data signal line 9L are coupled to bidirectional terminals of a bidirectional bus driver 10L. A clock output terminal and a data signal output terminal from the bidirectional bus driver 10L are coupled to corresponding input terminals of a receiver 20L. A bidirectional data terminal of the receiver 20L is coupled to a corresponding data terminal of a memory 30 via a data bus 25. The bidirectional data terminal of the memory 30 is also coupled to an input terminal of a transmitter 50L via the data bus 25. A clock output terminal of the transmitter SOL is coupled to a corresponding clock input terminal of the bidirectional bus driver 10L, and a data output terminal of the transmitter 50L is coupled to a corresponding data input terminal of the bidirectional bus driver 10L. A right hand connection point 5R is similarly coupled to the memory 30 via bidirectional bus driver 10R, receiver 20R and tranmitter 50R, and the data bus 25. A control logic circuit 90 provides a control signal for the left and right bidirectional bus drivers 10L and 10R, respectively.
The memory 30

REFERENCES:
patent: 4334288 (1982-06-01), Booher
patent: 4458314 (1984-07-01), Grimes
patent: 4803681 (1989-02-01), Takahashi
patent: 5081578 (1992-01-01), Davis
patent: 5124983 (1992-06-01), Landez et al.
patent: 5283904 (1994-02-01), Carson et al.
patent: 5398243 (1995-03-01), Aguilhon et al.
patent: 5418785 (1995-05-01), Olshanshy et al.
patent: 5487170 (1996-01-01), Bass et al.
patent: 5606556 (1997-02-01), Kawanishi et al.

Affiliated with

Also associated with

Rating

Digital data bus system including arbitration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital data bus system including arbitration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital data bus system including arbitration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1911746