Digital correction of nonlinearity errors of multibit...

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S118000, C341S143000, C341S144000

Reexamination Certificate

active

11430285

ABSTRACT:
Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.

REFERENCES:
patent: 5936561 (1999-08-01), Lee
patent: 6271781 (2001-08-01), Pellon
patent: 6313775 (2001-11-01), Lindfors et al.
patent: 6359575 (2002-03-01), Knudsen
patent: 6380874 (2002-04-01), Knudsen
patent: 6522276 (2003-02-01), Andre et al.
patent: 6611221 (2003-08-01), Soundarapandian et al.
patent: 7119725 (2006-10-01), Shih
patent: 7129874 (2006-10-01), Bjornsen
patent: 7176822 (2007-02-01), Schimper
Peter J. Naus, Eise Carel Dijkmans, Eduard F. Stikvoort, Andrew J. McKnight, David J. Holland and Wernver Bradinal, “A CMOS Stereo 16-bit D/A Converter for Digital Audio,”IEEE Journal of Solid-State Circuits, pp. 390-395, vol. SC-22, No. 3 (Jun. 1987).
T. Cataltepe, A.R. Kramer, L.E. Larson, G.C. Temes and R.H. Walden, “Digital Corrected Multi-Bit ΣΔ Data Converters,” pp. 647-650, Electrical Engineering Department UCLA (1989), no date, month.
L. Richard Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters,”IEEE Journal of Solid-State Circuits, pp. 267-273, vol. 24, No. 2 (Apr. 1989).
Bosco H. Leung and Sehat Sutarja, “Multibit Σ-Δ A/D Converter Incorporating A Novel Class of Dynamic Element Matching Techniques,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, pp. 35-51, vol. 39, No. 1 (Jan. 1992).
Mohammad Sarhang-Nejad and Gabor C. Temes, “A High-Resolution of Multibit ΣΔ ADC with Digital Correction and Relaxed Amplifier Requirements,”IEEE Journal of Solid-State Circuits, pp. 648-660, vol. 28, No. 6 (Jun. 1993).
Richard Schreier, “An Empirical Study of High-Order Single-Bit Delta-Sigma Modulators,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, pp. 461-466, vol. 40, No. 8 (Aug. 1993).
R. Schreier and B. Zhang, “Noise-shaped multi-bit D/A convertor employing unit elements,”Electronics Letters, pp. 1712-1713, vol. 31, No. 20 (Sep. 28, 1995).
Rex T. Baird and Terri S. Fiez, “Linearity Enhancement of Multibit ΔΣ A/D and D/A Converters Using Data Weighted Averaging,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, pp. 753-762, vol. 42, No. 12 (Dec. 1995).
Pervez M. Aziz, Henrik V. Sorensen and Jan Van Der Spiegel, “An Overview of Sigma-Delta Converters,”IEEE Signal Processing Magazine, pp. 61-84 (Jan. 1996).
Tom Kwan, Robert Adams and Robert Libert, “A Stereo Multibit ΣΔ DAC with Asynchronous Master-Clock Interface,”IEEE Journal of Solid-State Circuits, pp. 1881-1887, vol. 31, No. 12 (Dec. 1996).
Ian Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, pp. 808-817, vol. 44, No. 10 (Oct. 1997).
Un-Ku Moon, J. Silva, J. Steensgaard and G.C. Temes, “Switched-capacitor DAC with analogue mismatch correction,”Electronics Letters, pp. 1903-1904, vol. 35, No. 22 (Oct. 28, 1999).
Scott Willingham, Michael Perrott, Brian Setterberg, Andrew Grzegorek and Bill McFarland, “An Integrated 2.5GHz ΣΔ Frequency Synthesizer with 5 μs Settling and 2Mb/s Closed Loop Modulation,”2000 IEEE International Solid-State Circuits Conference, (2000).
Ian Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, pp. 185-196, vol. 47, No. 3 (Mar. 2000).
Craig Petrie and Matt Miller, “A Background Calibration Technique for Multibit Delta-Sigma Modulators,”IEEE International Symposium on Circuits and Systems, pp. II-29-II-32, (May 28-31, 2000, Geneva Switzerland).
Russ E. Radke, Aria Eshraghi and Terri S. Fiez, “A 14-Bit Current-Mode ΣΔ DAC Based Upon Rotated Data Weighted Averaging,”IEEE Journal of Solid-State Circuits, pp. 1074-1084, vol. 35, No. 8 (Aug. 2000).
X. Wang, P. Kiss, U. Moon, J. Steensgaard and G.C. Temes, “Digital estimation and correction of DAC errors in multibit ΔΣ ADCs,”Electronics Letters, pp. 414-415, No. 37, No. 7 (Mar. 29, 2001).
Peter Kiss, Jesus Arias, Dandan Li and Vito Boccuzzi, “Stable High-Order Delta-Sigma Digital-to-Analog Converters,”IEEE Transactions on Circuits and Systems—I: Regular Papers, pp. 200-205, vol. 51, No. 1 (Jan. 2004).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Digital correction of nonlinearity errors of multibit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital correction of nonlinearity errors of multibit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital correction of nonlinearity errors of multibit... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3925929

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.