Digital coordinator with smooth transition for offset changes

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340 40, 340 41R, G06F 1548

Patent

active

040619036

ABSTRACT:
An improvement in a digital coordinator of the type used for creating a background cycle defined by a series of control pulses repeatedly cycled between a first number, N.sub.1, and a second number, N.sub.2, with the time space between the N.sub.1 control pulse and the N.sub.2 control pulse being a background cycle length. This type of coordinator comprises a primary pulse counter means incremented by input counting pulses for creating one in a series of control pulses in response to a selected number of input counting pulses, wherein the input counting pulses have a selected frequency for determining the cycle speed of progression of the control pulses in successive count positions between the N.sub.1 control pulse and the N.sub.2 control pulse of a given background cycle, and shifting means for shifting the N.sub.1 control pulse with respect to time to correspond in time with a synchronization offset signal. The improvement in this type of coordinator includes means for digitally measuring the time period between the N.sub.1 control pulse and the occurrence of one of the synchronization offset signals during a given background cycle and further means for stopping the control pulses from the primary counter for the measured time period.

REFERENCES:
patent: 3252134 (1966-05-01), Auer et al.
patent: 3305828 (1967-02-01), Auer et al.
patent: 3483508 (1969-12-01), Cress et al.
patent: 3525980 (1970-08-01), Schmidt et al.
patent: 3537067 (1970-10-01), Ishikawa et al.
patent: 3551654 (1970-12-01), Arlen et al.

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