Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-01-03
2002-02-19
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000, C327S149000, C327S150000
Reexamination Certificate
active
06348823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a digital phase lock loop, and ore particularly, to a digital phase lock loop that generating output clock having wider frequency ranges than conventional approaches and no delay lookup circuit is required.
2. Description of the Prior Art
Phase lock loops (PLL) have been widely used in communication systems or the like, some frequently appeared applications such as extracting information from carried waves or synchronous signals usually employ PLLs to achieve their requirements. Typically, PLLs can be classified into analog- or digital-type PLL circuits.
FIG. 1
represents a schematic diagram of a conventional analog PLL, which basically consists of a phase detector
102
, a loop filter
104
, and a voltage controlled oscillator (VCO)
106
. Input signal S
ia
and the signal S
oa
output by the VCO
106
are together routed to the phase detector
102
for comparing their phases. An output voltage V
PD
according to the aforementioned comparison result is processed by the loop filter
104
to eliminate high frequency noises. A voltage V
LF
then outputs to VCO
106
for adjusting the currently oscillating frequency such that the phase deviation between S
ia
and S
oa
can be minimized. Typically, a low pass filter is usually used to construct the loop filter
104
because the high frequency signals will be removed in PLLs. However, analog circuits are very expensive because the loop filter
104
and VCO
106
are usually composed of resistance and capacitors conventionally, which also indicates that large spaces are occupied and required simultaneously. Nowadays, the advent of digital circuit technology brings the PLLs to be established by digital circuits such as flip-flops or logical gates (e.g., AND, OR, NOR, exclusive OR gates, and so on).
Please refer to
FIG. 2
, which shows a functional diagram representative of a conventionally digital PLL that includes an all-digital phase detector
202
, an all-digital loop filter
204
, a divider (DIV)
206
, a digitally controlled oscillator (DCO)
208
, and a fixed high frequency oscillator
210
. In operations, the input reference clock S
id
will be compared with the output clock of DIV
206
in all-digital phase detector
202
to obtain their phase differences. The comparison result is then processed by all-digital loop filter
204
to generate a control signal suitable for DCO
208
. The DCO
208
, which requires a reference clock generated by a fixed high frequency oscillator
210
, outputs a locked signal S
od
routed to DIV
206
for further processing instead of routed to all-digital phase detector
202
directly. DIV
206
that typically a programmable divider then divides the frequency of the reference clock provided from the fixed high frequency oscillator
210
before transferring to all-digital phase detector
202
. The fixed high frequency oscillator
210
is practically a crystal oscillator having a high oscillating frequency, which is usually provided for generating a reference clock for the system it mounted therein. In the present days, DCO
208
described above is broadly employed in digital PLLs to replace the use of VCO
106
in analog PLLs, many schematics for DCO
208
are thus disclosed today. Descriptions of some structures associated with the invention are given hereinafter.
Please refer to
FIG. 3A
, which depicts a schematic diagram composed of fractional structure to generate the desired clock by dividing reference clock having high frequency conventionally. A waveform diagram generated by the structure of
FIG. 3A
is depicted in
FIG. 3B. A
clock CK_OSC generated by a fixed high frequency oscillator
302
is used as the base for generating an output clock S
OF
by the cooperation of a divider (DIV)
304
, a fractional part set
306
, and a selector
308
. In operations, the relation between the frequency F
CK
—
OSC
of CK_OSC and the frequency F
CK
—
DCO
of the target clock can be described as:
F
CK_DCO
×
N
A
M
=
F
CK_OSC
where A and M are internally controlled parameters of the fractional structure. For example, when F
CK
—
OSC
and F
CK
—
DCO
are respectively 32 and 13 MHz, the above equation will be:
F
CK_DCO
×
N
A
M
=
F
CK_OSC
=
32
=
13
×
2
6
13
Thus, A, M and N are 6, 13, and 2, respectively. In operations, the fractional part set
306
generates a comparison result S
D
to decide the frequency next output through S
OF
by using parameters A and M when triggered by S
OF
. For example, when M and F
CK
—
OSC
are respectively 13 and 32 MHz, a clock having an average frequency of 13 MHz can be derived by using clocks of 16 and 10.67 MHz because 13 falls in a range of 16 MHz(32/2) to 10.67 MHz(32/3). At the beginning, a clock having a frequency equal to a half of F
CK
—
OSC
(i.e., 16=32/N, N=2) can be output as S
OF
because A (6) is smaller than M (13). At the second period, the clock having a frequency equal to a half of F
CK
—
OSC
is still output as S
OF
because A plus itself (i.e., A=6) to obtain 12 which is also smaller than M (13). Next at the third period, due to the added value becomes 18 (12+6) is larger than M, the fractional part set
306
outputs an overflow signal to force the selector
308
to output a clock having a frequency of 10.67 (32/(2+1)) MHz as S
OF
. Additionally, control signals from the loop filter
204
can adjust the frequency of S
OF
, for example, a carry signal or a borrow signal can slow down or speed up the output clock S
OF
, respectively.
A very simple structure is obviously offered by
FIG. 3A
to generate a clock having an average frequency equal to the target clock. Accordingly, the manufacture cost can be significantly degraded based on fractional structure, and furthermore the duty cycle of the generated clock is 100%. However, the output jitter generated by the fractional structure usually too large to make the systems abnormally perform. Please refer to
FIG. 3B
again, the output jitter will be larger when the frequencies of the target clock and F
CK
—
OSC
are getting closer because the frequency of S
OF
switches at (F
CK
—
OSC
×1/N) and (F
CK
—OSC
×1/(N+1)). For example, S
OF
will varies from 10.67 to 16 MHz when N=2. However, S
OF
will varies from 16 to 32 MHz when N=1, and the output jitter will be:
1
/N−
1(
N
+1)=1/1−1/2=1/2
UI
(Unit Interval)
which is usually out of the current jitter specification (e.g., 1/8 or 1/6 UI). On the other hand, the period of the clock generated by the fractional structure is unstable although its average frequency coincide the jitter specification of the target clock such as period indicated by a label
310
in FIG.
3
B. The system applied the fractional structure may occasionally abnormally work because the unstable period may result in some elements of the system work abnormally. Accordingly, the fractional structure are typically employed in those applications that the frequency difference between reference clock and target clock is larger enough, for example, 100 and 32 MHz, respectively. It is especially unsuitable to use the fractional structure for the other applications that quick clocks are desired.
The second DCO structure is so-called phase-hopping DCO structure,
FIGS. 4A and 4B
respectively illustrates the schematic and timing diagram according to the conventional phase-hopping structure. The phase-hopping structure shown in
FIG. 4A
basically encompasses a fixed high frequency oscillator
402
, a divide-by-N divider (DIV)
404
, an L-tapped delay line
406
, a multiplexer (MUX)
408
, an adder
410
, a log
2
(L)-bits latch
412
, and an L-to-1 MUX. In operations, DIV
404
generates the target clock whose frequency equals to the quotient of F
CK
—
OSC
dividing by an integer. For example, an oscillator
402
of 32 MHz clock can be divided by an integer
16
to obtain a target clock of 2 MHz. Output of the DIV
404
is routed into the log
2
Cunningham Terry D.
Industrial Technology Research Institute
Morgan & Finnegan , LLP
Tra Quan
LandOfFree
Digital controlled oscillating circuit of digital phase lock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital controlled oscillating circuit of digital phase lock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital controlled oscillating circuit of digital phase lock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2973451