Digital control apparatus for the running speed of a motor vehic

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Details

180179, 364565, G05D 1358, B60K 3100

Patent

active

043375111

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to a speed control apparatus for a motor vehicle.
Such a control apparatus is already known from DE-OS 2 546 529 (corresponds to U.S. Pat. No. 4,098,367), in which the new demand value is suddenly issued during changes of the running speed. Since the running speed reacts relatively sluggishly, there may occur control fluctuations which extend over several periods after the new demand value is reached. In order to decrease such overshoot, it is known from DE-OS 2 537 415 (corresponds to U.S. Pat. No. 4,094,378) to employ a controller with a PD-characteristic. However, a PD or P-controller causes the controlled speed to become inaccurate after the setting process due to differing loads and variable play in the positioning member linkage. By contrast, if an I-controller is used, one obtains poorer driving comfort.


SUMMARY OF THE INVENTION

The apparatus according to the invention has the relative advantage that the error becomes O after every setting process and that a soft transition can be accomplished through the transformation of the actual value into a demand-value differing therefrom, by means of a pre-programmed ramp function. The slow ramp function delays the ramp value until the actual value equals the demand value. The ramp value is then locked in as the demand value. By these means, all influences on the setting process are eliminated.
The use of a ramp function having two differing slopes wherein a relatively larger first slope is transformed into a relatively smaller slope at the end of the ramp, or a ramp function having a continuously decreasing slope is especially advantageous, and results in an even softer transition to the new running speed.
Optimal conditions are attained through the use of a microcomputer, preferably a 1-chip micro-computer. In this manner, the digital control apparatus is realizable very simply and price-favorably in small production volumes.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit representing a first exemplary embodiment of the invention with a setting control circuit;
FIG. 2 is a diagram representing an acceleration process carried out by the control apparatus of FIG. 1;
FIG. 3 is a diagram illustrating the process of the transformation of the running speed to a previously stored demand value;
FIG. 4 is a circuit representing a second exemplary embodiment of the invention without a setting control circuit;
FIG. 5 is a diagram similar to FIG. 3 for the second exemplary embodiment;
FIG. 6 is a diagram depicting the same process for the case of an inclined road;
FIG. 7 is a circuit representing a setting device embodied as a pulse controller;
FIG. 8 is a diagram explaining the functioning of the pulse controller of FIG. 7; and
FIG. 9 is a circuit design of an initializing device.


DETAILED DESCRIPTION

In the exemplary embodiment depicted in FIG. 1, a connector 10 at positive potential is connected via a main switch 11 controlling the voltage supply to five switching devices 12 to 16 preferably consisting of push button switches. The switches 12 and 13 are embodied as the brake switch and the clutch switch, respectively, and are closed when the mechanically interconnected brake or clutch is activated. Each of the switches 12, 13 is connected to a respective input of an OR-gate 17 whose output is connected both to an input of a further OR-gate 18 and to the Set-input S of a flipflop 19. The switches 14 to 16 are the command switches of the control apparatus. The first switch 14 constitutes a resumption switch, which permits a previously stored demand running speed to be resumed upon its actuation. The second switch 15 constitutes the deceleration switch and the third switch 16 constitutes the acceleration switch; i.e., a deceleration or an acceleration takes place upon actuation of one of these switches. The switches 15, 16 also serve for the storage and retention of the instantaneous running speed.
Each of the switches 14 to 16 is connected to one input of an OR-gate 20 as well as to three AND-gates 21

REFERENCES:
patent: 3869019 (1975-03-01), Cardani
patent: 3885137 (1975-05-01), Ooya et al.
patent: 3891046 (1975-06-01), Oicles
patent: 3941202 (1976-03-01), Sorkin
patent: 3952829 (1976-04-01), Gray
patent: 4046213 (1977-09-01), Larson
patent: 4072206 (1978-02-01), Larson et al.
patent: 4094378 (1978-06-01), Scheyhing et al.
patent: 4098367 (1978-07-01), Fleischer
patent: 4138723 (1979-02-01), Nehmer et al.
patent: 4140202 (1979-02-01), Noddings et al.
patent: 4196787 (1980-04-01), Sakakibara et al.

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