Digital communication systems

Details Digital communication systems Digital communication systems

1974-09-19

1976-02-03

Atkinson, Charles E.

Telegraphy

Systems

Line-clearing and circuit maintenance

178 88, 179 15A, 235 92TF, 235 92CC, 325322, H04B 116, H04L 1524, G06G 700

Patent

active

039366030

ABSTRACT:
A digital phase locked loop is described which includes a first gate through which incoming pulses are passed to subsequent data processing circuits, a second gate through which reference pulses having a predetermined pulse repetition rate equal to the repetition rate of the wanted incoming pulses are fed to a reset input of a counter such that each reference pulse resets the counter to zero, and a clock generator for feeding clock pulses to the counter. The counter is thereby repeatedly stepped through a predetermined cycle, the nominal period of the counter cycle being equal to the nominal period of the reference pulses, and means responsive to the number stored in the counter reaching a first predetermined value then latches both the first and second gates open for a predetermined relatively short period in each counter cycle during which the counter passes through its zero state.

REFERENCES:
patent: 2799727 (1957-07-01), Segerstrom
patent: 3133189 (1964-05-01), Bagley et al.
patent: 3593160 (1971-07-01), Moore
patent: 3767902 (1973-10-01), Estes et al.

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