Digital communication system fault isolation circuit

Details Digital communication system fault isolation circuit Digital communication system fault isolation circuit

1979-11-15

1981-07-14

Robinson, Thomas A.

Excavating

1791753S, 340147SC, H04Q 900, G08C 2500

Patent

active

042790344

ABSTRACT:
There is disclosed, for use in a digital communication system, a fault detector circuit operable for removing faulty stations from the system. The disclosed circuit uses a distributed bypass isolation technique and may be used with individual stations or with groups of stations. A multi-bit delay register is connected across each station or station group and the output of the delay register is compared with the output of the parallel stations. When differences in the compared bits are detected the parallel stations are immediately isolated from the system and the bits from the delay register are placed in the system to preserve synchronism. This arrangement has the advantage of allowing immediate corrective action to occur to protect the sanity of the system. In situations where the system is divided into a voice digital bus and a data digital bus different error techniques may be employed for each bus.

REFERENCES:
patent: 3409875 (1968-11-01), De Jager et al.
patent: 3526837 (1970-09-01), Zegers et al.
patent: 4159470 (1979-06-01), Strojny et al.

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