Digital communication demodulator, digital communication demodul

Pulse or digital communications – Receivers – Angle modulation

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Details

375344, 4551822, 4551851, 4551922, 348731, 348735, H04L 2706

Patent

active

059870745

ABSTRACT:
A demodulator and a demodulation method are designed so as to reduce the load of a CPU. A host CPU controls a digital demodulation circuit, an error correction circuit, a transport circuit and an MPEG decoder through a bus. The host CPU outputs a control signal to a format conversion circuit via a CPU interface when it instructs a tuner to perform tuning. The format conversion circuit converts the format of this control signal into a 3-wire format and outputs the converted signal to a frequency divider of the tuner.

REFERENCES:
patent: 5125106 (1992-06-01), Kato
patent: 5699384 (1997-12-01), Dillon
patent: 5826166 (1998-10-01), Brooks et al.
patent: 5845200 (1998-12-01), Suzuki et al.

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