Digital clock timing generation in a spread-spectrum digital com

Details Digital clock timing generation in a spread-spectrum digital com Digital clock timing generation in a spread-spectrum digital com

1991-06-03

1993-01-05

Gregory, Bernarr E.

Pulse or digital communications

Repeaters

Testing

380 34, H04L 2730

Patent

active

051777665

ABSTRACT:
A unique method and system is disclosed for generating digital clock timing in a receiver for use in direct-sequence spread-spectrum digital communication systems wherein spread data is delivered from a transmitter to a receiver. The present invention provides at the transmitter frames of digital communication data with each frame having a plurality of time slots and with each time slot having a plurality of digital bits. The transmitter utilizes direct-sequence spreading codes for spreading the digital bits in the time frame. The direct sequence spreading codes each have the same fixed sequence length of M chips and, furthermore, the number of chips per bit CB to spread each digital bit is constant and fully aligned with each digital bit. The ration of M:CB is an integer and the ratio of time of each time slot to the time of the M chips also equals an integer. The spread frames of digital information are despread at the receiver with receiver provided identical direct-sequence codes. The digital clock timing is generated from the receiver's pseudo random sequence generator. Bit timing equals CB*8, nibble timing equals 4*CB, and byte timing equals CB.

REFERENCES:
patent: 4017798 (1977-04-01), Gordy et al.
patent: 4383322 (1983-05-01), Halpern et al.
patent: 4918707 (1990-04-01), Yoshihara
patent: 5093841 (1992-03-01), Vancraeynest

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