Digital clock smoothing

Details Digital clock smoothing Digital clock smoothing

2011-08-09

2011-08-09

Sheikh, Ayaz R (Department: 2476)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C375S372000

Reexamination Certificate

active

07995622

ABSTRACT:
A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.

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U.S. Appl. No. 11/357,685, Office Action dated Dec. 30, 2008, 11 pages.
U.S. Appl. No. 11/357,685, Notice of Allowance dated Dec. 30, 2008, 4 pages.

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