Digital clock signal multiplier circuit

Details Digital clock signal multiplier circuit Digital clock signal multiplier circuit

1993-07-28

1995-06-06

Envall, Jr., Roy N.

Boots, shoes, and leggings

G06F 752

Patent

active

054228352

ABSTRACT:
A digital clock signal multiplier circuit for generating an on-chip clock signal having a higher frequency than a system clock signal. A variable delay line, coupled to receive the system clock signal, is partitioned into (N) equal segments with each segment having multiple delay elements. Each of the delay elements is tapped to allow selective output of a corresponding delay signal. Multiple control switches, each associated with one of the delay elements, provide selective control for issuance of only one delay signal from each segment of the variable delay line. Delay signals selected for output are symmetrically offset and are fed to (N) pulse generators for the production of (N) pulse signals of duration substantially less than the period of the external clock signal. An output generator is coupled to receive the pulse signals output from the (N) pulse generators and produce therefrom the internal clock signal of desired frequency. Control circuitry selects the delay signals output from the (N) equal segments via appropriate activation of the associated control switches.

REFERENCES:
patent: 3673391 (1972-06-01), Lougheed
patent: 4773031 (1988-09-01), Tobin
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5010561 (1991-04-01), Itoh
patent: 5059838 (1991-10-01), Motogi et al.
patent: 5179294 (1993-01-01), Bechade et al.
patent: 5260608 (1993-11-01), Marbot

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