Digital clock recovery PPL

Details Digital clock recovery PPL Digital clock recovery PPL

2005-12-20

2005-12-20

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S363000, C360S032000, C386S349000

Reexamination Certificate

active

06977975

ABSTRACT:
An apparatus comprising an analog circuit, a first digital circuit, and a second digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The first digital circuit may be configured to generate (i) one or more data signals, (ii) a first strobe signal, and (iii) a second strobe signal in response to the plurality of samples, the plurality of phases, and a correction signal. The second digital circuit may be configured to generate the correction signal and a width signal in response to (i) the one or more data signals, (ii) the first strobe signal, and (iii) the second strobe signal.

REFERENCES:
patent: 6266799 (2001-07-01), Lee et al.
patent: 6417698 (2002-07-01), Williams et al.
David R. Reuveni, “Digital Clock Recovery PLL”, U.S. Appl. No. 09/822,112, filed Mar. 30, 2001.
David R. Reuveni, “Digital Clock Recovery PLL”, U.S. Appl. No. 09/822,041, filed Mar. 30, 2001.

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