Digital clock recovery loop

Details Digital clock recovery loop Digital clock recovery loop

2000-07-05

2001-09-04

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S025000, C331S078000, C327S157000, C327S159000, C375S376000

Reexamination Certificate

active

06285261

ABSTRACT:

TECHNICAL FIELD
This invention relates to communications systems. More particularly, the invention relates to phase locked loops employed in communications systems.
BACKGROUND OF THE INVENTION
Phase locked loops are known in the art. A phase locked loop is a circuit containing an oscillator whose output phase and/or frequency is steered to keep it in synchronization with some reference signal. A phase locked loop typically includes a phase comparator having a first input receiving an input reference signal, having a second input, and having an output, a filter having an input receiving the output of the phase comparator and having an output, an amplifier having an input receiving the output of the filter, and having an output defining the output of the phase locked loop, and a voltage controlled oscillator having an input receiving a control voltage from the amplifier and having an output connected to the second input of the phase comparator.
Phase locked loops have various applications. In many communications systems, for example, it is necessary to recover a clock signal from the received data. A phase locked loop is one way of recovering such a clock signal.
SUMMARY OF THE INVENTION
The invention provides a digital clock recovery loop. The digital clock recovery loop includes a voltage controlled oscillator. The voltage controlled oscillator has an output, and produces a square wave at output having a frequency controlled by the voltage on an input control node. In one embodiment, only one control node is employed; however, the illustrated embodiment, a differential control node scheme is employed involving two control nodes. Therefore, in the illustrated a embodiment, a capacitor is provided on each control node, and control voltages are stored in analog form on these two capacitors. When the voltage on the control node is zero, the frequency at output is at least one half of the final recovered frequency and not greater than the final recovered frequency. The output frequency rises monotonically, nearly linearly, as the control node voltage is increased.
The digital clock recovery loop further includes a charge pump and loop filters which control the rate of change of the voltage on the control node of the voltage controlled oscillator.
The digital clock recovery loop further includes a startup circuit which performs frequency detection when the voltage controlled oscillator first starts up and, in conjunction with the charge pump and loop filters, causes the voltage on the control node of the voltage controlled oscillator to change rapidly.
The digital clock recovery loop further includes a state machine which performs phase detection when the frequency of the voltage controlled oscillator is within a few percent of its final value and, in conjunction with the charge pump and loop filters, causes the voltage on the control node of the voltage controlled oscillator to change slowly.
The only analog blocks are the voltage controlled oscillator and the charge pump. The rest of the circuits of the digital clock recovery loop are digital circuits which are easy to build at high yield in integrated circuit processes.


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