Digital clock recovery circuit for return to zero data

Details Digital clock recovery circuit for return to zero data Digital clock recovery circuit for return to zero data

1986-10-02

1987-09-22

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375110, H04L 702

Patent

active

046960163

ABSTRACT:
A digital clock recovery circuit is described which extracts the signal element timing from a return-to-zero data stream. A converter changes the bipolar digital data stream to at least one first return-to-zero data stream representing pulses in the bipolar digital data stream. In these streams, a logic one is typically represented by a pulse of undetermined width less than the bit period. A logic zero is typically represented by no pulse. A reference clock signal having a predetermined frequency is required by the circuitry. An edge detector detects the positive going edges of the pulses in the combined return-to-zero data stream, and generates load pulses to a counter which are synchronized to transitions of the reference clock signal. The counter receives the load pulses and utilizes reference clock signal to produce a recovered clock signal, skiping or repeating counter states to kepp the recovered clock signal aligned with the bipolar digital data stream.

REFERENCES:
patent: 3108265 (1963-10-01), Moe
patent: 3688036 (1972-08-01), Bland
patent: 4282601 (1981-08-01), Flora

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