Digital clock recovery circuit apparatus

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307479, 307262, 307511, 307518, 307527, 328 63, 328 72, 328109, H03K 3017, H03K 117

Patent

active

047000848

ABSTRACT:
A circuit for using a high speed clock and a counter to obtain a recovered clock with incoming data resetting the counter whenever a logic "1" of more than a predetermined number of high speed clocks is received. Further, the presence of a data out logic "1" inhibits the reaction of the circuit to any further input pulses during the time necessary to generate the retimed data output logic "1".

REFERENCES:
patent: 3755748 (1973-08-01), Carlow et al.
patent: 3894246 (1975-07-01), Torgrim
patent: 4025866 (1977-05-01), Fletcher et al.
patent: 4641044 (1987-02-01), Shiraishi

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