Digital clock recovery

Details Digital clock recovery Digital clock recovery

1998-04-28

2004-03-30

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

06714548

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method and apparatus for digital clock recovery, in particular for a packet oriented network environment.
BACKGROUND OF THE INVENTION
An example of a packet oriented transmission technology for the realization of Broadband Integrated Service Networks (BISDN) is the technology called Asynchronous Transfer Mode (ATM). This permits services as diverse as voice, data and video to be transmitted through the same medium and in the same format. The transport of constant bit rate (CBR) data over an ATM network is usually referred to as circuit emulation. The accommodation of constant bit rate (CBR) services by ATM is particularly important, for compatibility with existing systems and future networks, even if ATM is more suitable to the transport of bursty traffic, such as data. One of the critical issues of circuit emulation is the recovery of clock frequency of the source data (the service clock frequency) at the receiver.
ATM's basic transport entity is a 53 byte cell. Five of these bytes are header bytes, and convey information such as link-to-link routing, error correction, service information (priority, payload identifier), and cell type identification. A protocol stack is defined by ITU-T for ATM technology, in which the so-called ATM layer performs operations typically found in layers 2 and 3 of the OSI model. Above the ATM layer is an ATM adaptation layer (AAL), which is divided into segmentation and reassembling layers (SAR) and a convergence sublayer (CS). Five different types of AAL have been defined by ITU-T, covering various applications. The AAL-1 (ATM Adaptation Layer 1) is devoted to CBR services. Of the 48 remaining information bytes of an ATM cell, one used by the AAL1 SAR for functions including timing recovery and cell loss detection which leaves 47 data bytes (376 bits). To transport a CBR service into an ATM network, the data is segmented into cells of 47 bytes, an SAR byte is then added to each cell, the 48 bytes are mapped in an ATM cell and are then sent through the network.
As a result of statistical multiplexing of cells at the source and of queuing delays incurred in ATM switches, successive cells arrive to the destination aperiodically. The deviation from ideal arrival time is called cell jitter or cell delay variation (CDV). It obviously increases with the network load, as queuing delays are functions of the switch load. Cell jitter is composed of a relatively high frequency stuffing jitter and of a low frequency waiting time jitter. The problem with cell jitter is that it can be very large, and except for the fact that its average is zero, its characteristics are mostly unknown.
The ITU-T has set output clock jitter recommendations whereby the frequency shift at 2.048 MHz on emission clocks is +/−50 ppm (1 ppm=1 part per million=2.048 Hz shift).
In order to achieve clock recovery, the exact service frequency should be recovered at the receiver. However, this is not straightforward due to the problems of output jitter and wander control. Jitter is defined as the higher frequency characteristics of a phase variation on a given clock signal. Wander is the lower frequency part of this phase variation. Both are commonly measured in terms of unit intervals (UI), where one UI corresponds to one cycle of the clock signal. ITU-T recommendation G.823 has precisely defined output jitter limits that must be met if the system is to be compatible with any CBR equipment. The bounds on maximum peak-to-peak output jitter for 2.048 Mbits.s
−1
CBR services are shown in Table 1.
TABLE 1
Frequency
20 Hz-18 kHz
18 kHz-100 kHz
Jitter
1.5 UI
0.2 UI
Wander tolerance is not as well defined as output jitter. However, input jitter should not be greater than 36.9 UI under 1.2×10−5 Hz.
Two techniques are known for recovering a service, or emission clock at a receiver. A first technique, known as the “adaptive method”, recovers the service clock based on the fill-level of a incoming cell buffer. A second technique, known as the “synchronous method” is based on the availability of a common network reference clock between the source and the end equipment.
The common clock used in the synchronous method is distributed by the network, and is available by means of either the so-called Synchronous Digital Hierarchy (SDH) network or its North American version Synchronous Optical NETwork (SONET). As not all CBR equipment is able or willing to be synchronized at the network clock, a method exists to perform CBR transmission at any rate, using this network clock. The method which was first proposed by Bell Laboratories and then adopted by ITU-T is the so-called synchronous residual time stamps (SRTS) technique. This allows transmission at any given bit rate.
The SRTS technique uses the network common clock to generate a unique number (the SRTS, or Synchronous Residual Time Stamp) which, on receipt, is used to recover the service clock. This information is inserted into the SAR byte (the 48th byte) and sent to an ATM cell. Using this common clock completely eliminates the cell jitter problem, as the actual cell arrival instants are not taken into account when recovering the service clock.
FIG. 1
of the accompanying drawings is a schematic block diagram illustrating an example of an SRTS signal generator
10
.
The service clock
12
(at frequency fs) is divided by an integer N in a first divider
16
. The integer N represents the SRTS period and is typically a multiple of 376, as an ATM cell conveys
47
information bytes, that is 47×8=376 bits. ITU-T recommends that the SRTS
24
is coded on 4 bits. As the SRTS is transported by the SAR byte, and only one bit every two cells can be devoted to SRTS, 8 cells are necessary to convey one time stamp, which leads to a preferred value of N=8×376=3008. The output of the first divider
16
is used as a latching signal to a latch
20
for latching the output of a p-bit free running counter
22
, driven by a submultiple fnx of the network clock
14
. The output of the latch
20
forms the SRTS
24
.
The submultiple fnx of the network clock is generated by dividing the network clock
14
(at the network frequency fn) by a divider x in a second divider
18
. The division ratio x is chosen so that the ratio fs/fnx stays over 1 but under 2 in order to reduce jitter and wander on the recovered clock. The value of the network clock depends on the type of network. For SDH network, fn is 155.52 MHz, so fnx will be of the form 155.52/2
k
. For 2.048 MHz clock recovery, k equals 6, and fnx 2.43 MHz. The SONET network referenced above distributes a 51.84 MHz clock, which leads to a value for fnx of 3.24 MHz.
During a SRTS period (=Nfs clock periods), there are M cycles of the fnx clock. Generally, M is not an integer. The information conveyed by the SRTS
24
is the number of cycle slips between the two clocks at frequency fs and fnx, modulus 2p over a SRTS period (=N periods of the fs clock), rounded towards zero. The residual part, corresponding to the fact that M is not an integer, accumulates until it reaches unity.
FIG. 2
of the accompanying drawings is a schematic block diagram of an SRTS receiver
30
for implementing a known technique to recover the service clock using the SRTS
24
. The SRTS receiver
30
comprises an SRTS buffer
32
in which received SRTSs are buffered. An output
24
from the SRTS buffer
32
is supplied to one input of a comparator
34
. The other input to the comparator is connected to the output of a free running p-bit counter
36
(locally generated SRTS) which is driven by an fnx clock
38
. The output of the comparator and the fnx clock are supplied to a gating circuit
40
. The output of the gating circuit is supplied to a phase locked loop (PLL)
42
. The output of the PLL
42
forms the clock fs.
In order to illustrate the operation of the SRTS receiver
30
of
FIG. 2
, it is assumed that the PLL
42
is locked, the gating circuit
40
has just been reset, and a new SRTS
24
has ju

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