Digital clock pulse positioning circuit for delaying a signal in

Details Digital clock pulse positioning circuit for delaying a signal in Digital clock pulse positioning circuit for delaying a signal in

1994-10-03

1996-08-20

Lee, Thomas C.

Pulse or digital communications

Repeaters

Testing

39520019, 395550, 395878, 375242, 364270, 3642703, 3642715, G06F 104, G06F 1314

Patent

active

055487971

ABSTRACT:
An input/output channel controller includes a storage array for temporarily storing data and multiple clocks to access or update the data. One or more array clock signals are generated from a system clock combined with other clock signals to generate a single clock signal which is positioned in time by a clock positioning circuit to accommodate circuit throughput delay variations and to effectively reduce hold time to zero. Storage arrays may be clocked at significantly higher frequencies and arrays may have multiple gated clocks without incurring the hold time problems.

REFERENCES:
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patent: 4802120 (1989-01-01), McCoy
patent: 4899273 (1990-02-01), Omoda et al.
patent: 5008636 (1991-04-01), Markinson et al.
patent: 5233615 (1993-08-01), Goetz
patent: 5305452 (1994-04-01), Khan et al.
patent: 5367204 (1994-11-01), Mattison
patent: 5396598 (1995-03-01), Anderson et al.

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