Digital clock multiplier and divider with output waveform...

Details Digital clock multiplier and divider with output waveform... Digital clock multiplier and divider with output waveform...

2000-11-14

2002-09-03

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S152000, C327S115000, C327S116000

Reexamination Certificate

active

06445232

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a digital clock multiplier and divider, which can easily be integrated into digital circuits.
BACKGROUND OF THE INVENTION
Clocking signals are used for a variety of purposes in digital circuits on both board level systems and integrated circuit (IC) devices, such as field programmable gate arrays (FPGAs) and microprocessors. For example, in synchronous systems, global clock signals are used to synchronize various circuits across the board or IC device. However, as the complexity of digital systems increases, clocking schemes for synchronous systems become more complicated. For example, many complex digital systems, such as microprocessors and FPGAs, have multiple clock signals at different frequencies. For example, in some microprocessors, internal circuits are clocked by a first clock signal at a first clock frequency while input/output (I/O) circuits are clocked by a second clock signal at a second clock frequency. Typically, the second clock frequency is slower than the first clock frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals; however, clock generating circuits typically consume a large amount of chip or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from a reference clock signal. Typically, clock dividers divide the frequency of the reference clock signal by an integer value. Conversely, clock multipliers are used to generate one or more clock signals of higher clock frequencies from the reference clock signal. Combining clock multipliers with clock dividers provide clocking circuits which can generate one or more clock signals having frequencies that are fractional values of the frequency of the reference clock signal.
FIG. 1
shows a conventional clocking circuit
100
. Clocking circuit
100
receives a reference clock signal REF_CLK having a frequency F_REF and generates an output clock signal O_CLK having a frequency F_OUT, where F_OUT is equal to frequency F_REF multiplied by a multiplier M and divided by a divider D, i.e., F_OUT=F_REF*M/D. Clocking circuit
100
comprises a clock divider
105
, a frequency comparator
110
, a charge pump
120
, a voltage controlled oscillator (VCO)
140
, and a clock divider
150
. Clock divider
105
divides reference clock signal REF_CLK to generate a divided reference clock signal D_REF_CLK having a frequency F_D_REF equal to frequency F_REF divided by D. Similarly, clock divider
150
divides output clock signal O_CLK to generate a feedback clock signal FBK_CLK having a frequency F_FBK equal to frequency F_OUT divided by M. Reference clock signal REF_CLK may be referred to as the primary reference clock signal.
Frequency comparator
110
compares frequency F_FBK of feedback clock signal FBK_CLK with frequency F_D_REF of divided reference clock signal D_REF_CLK. If frequency F_FBK of feedback clock signal FBK_CLK is greater than frequency F_D_REF of divided reference clock signal D_REF_CLK, frequency comparator
110
causes charge pump
120
to decrease the voltage level of VCO control signal VCO_C, which is coupled to voltage controlled oscillator
140
, to reduce frequency F_OUT of output clock signal O_CLK, which is generated by voltage controlled oscillator
140
. Conversely, if frequency F_FBK of feedback clock signal FBK_CLK is less than frequency F_D_REF of divided reference clock signal D_REF_CLK, frequency comparator
110
causes charge pump
120
to increase the voltage level of VCO control signal VCO_C to increase frequency F_OUT of output clock signal O_CLK. Thus, eventually, frequency F_FBK of feedback clock signal FBK_CLK equals frequency F_D_REF of divided reference clock signal D_REF_CLK. As explained above, frequency F_D_REF of divided reference clock signal D_REF_CLK is equal to frequency F_REF of reference clock signal REF_CLK divided by D, i.e., F_D_REF=F_REF/D. Similarly, as explained above, frequency F_FBK of feedback clock signal FBK_CLK is equal to frequency F_OUT of output clock signal O_CLK divided by M, i.e., F_FBK=F_OUT/M. Thus, frequency F_OUT of output clock signal O_CLK is equal to frequency F_REF of reference clock signal REF_CLK multiplied by M and divided by D, i.e., F_OUT=F_REF*M/D.
While clocking circuit
100
provides the desired functionality of a clock multiplier/divider, clocking circuit
100
is hampered by the use of analog components, which require a large amount of semiconductor area. Specifically, charge pump
120
and voltage controlled oscillator
140
are analog circuits, which increase the cost of clocking circuit
100
due to increased semiconductor real estate. Furthermore, analog circuits are more susceptible to electromagnetic interference (i.e., noise) as compared to digital circuits. Hence, there is a need for a variable clock multiplier/divider using only digital circuits, which generates an output clock signal having a clock frequency equal to the clock frequency of a reference clock signal multiplied by a multiplier M and divided by a divider D.
SUMMARY
Accordingly, variable clocking circuits in accordance with the present invention are created using variable digital oscillators and digital control circuits to generate an output clock signal having a clock frequency equal to the clock frequency of a reference clock signal multiplied by a multiplier M and divided by a divider D. When the frequency of the output clock signal is equal to the selected frequency and the output clock signal is in phase with the reference clock signal, every Mth rising edge of the output clock signal O_CLK aligns with a rising edge of the reference clock signal. The alignments are commonly referred to as concurrences. The time between two consecutive concurrences is commonly referred to as a concurrence period. The present invention avoids cumulative rounding errors caused by the imprecision of digital delay lines by synchronizing the output clock signal with the reference clock signal at each concurrence. Furthermore, a circuit according to one embodiment of present invention shapes the waveform of an output clock signal by selectively inserting delays during a concurrence period.
In one embodiment of the present invention, a variable clocking circuit includes a variable oscillator, a first clock divider, and a frequency comparator. The variable oscillator generates the output clock signal. The first clock divider divides the output clock signal by M and generates a feedback clock signal. The frequency comparator, which receives both the reference clock signal and the feedback clock signal, adjusts the frequency of the output clock signal so that the frequency of the feedback clock signal is approximately equal to the frequency of the reference clock signal. To eliminate cumulative rounding errors from using digital circuits, the active edges of the output clock signal occurring during a concurrence are synchronized with the active edge of the reference clock signal. Generally, the variable oscillator includes a variable delay line and an edge-triggered latch. The edge triggered latch is clocked by the output of the delay line except during a concurrence. During a concurrence the edge-triggered latch is clocked by the reference clock signal.
Some embodiments of the present invention include a delay line fine tuning controller to shape the waveform of the output clock signal to more accurately match the waveform of an ideal output clock signal. The delay line fine tuning controller-determines the number of additional base delay units necessary during a concurrence period. The additional base delay units. are then distributed evenly across the concurrence period. The distribution is accomplished by using a novel modulo-M delta sigma cir

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