Digital clock manager having cascade voltage switch logic...

Details Digital clock manager having cascade voltage switch logic... Digital clock manager having cascade voltage switch logic...

2006-05-02

2006-05-02

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S285000

Reexamination Certificate

active

07038519

ABSTRACT:
A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

REFERENCES:
patent: 5068628 (1991-11-01), Ghoshal
patent: 5374860 (1994-12-01), Llewellyn
patent: 5465076 (1995-11-01), Yamauchi et al.
patent: 5489864 (1996-02-01), Ashuri
patent: 5638030 (1997-06-01), Du
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5712884 (1998-01-01), Jeong
patent: 5796673 (1998-08-01), Foss et al.
patent: 5963074 (1999-10-01), Arkin
patent: 5994938 (1999-11-01), Lesmeister
patent: 6043717 (2000-03-01), Kurd
patent: 6104223 (2000-08-01), Chapman et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6151356 (2000-11-01), Spagnoletti et al.
patent: 6184753 (2001-02-01), Ishimi et al.
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6211722 (2001-04-01), Mattia et al.
patent: 6289068 (2001-09-01), Hassoun et al.
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 6400180 (2002-06-01), Wittig et al.
patent: 6400735 (2002-06-01), Percey
patent: 6492851 (2002-12-01), Watarai
patent: 6501309 (2002-12-01), Tomita
patent: 6518812 (2003-02-01), Sikkink et al.
patent: 6621358 (2003-09-01), Carballo et al.
patent: 6642771 (2003-11-01), Smetana
patent: 6847246 (2005-01-01), Kaviani et al.
patent: 0655840 (1994-11-01), None
patent: 0704975 (1996-04-01), None
patent: 5-191233 (1993-07-01), None
patent: WO97/40576 (1997-10-01), None
patent: WO99/14759 (1999-03-01), None
patent: WO 99/67882 (1999-12-01), None
U.S. Appl. No. 10/792,055, filed Mar. 2, 2004, Lu.
U.S. Appl. No. 10/618,404, filed Jul. 11, 2003, Young.
U.S. Appl. No. 10/837,210, filed Apr. 30, 2004, Percey, et al.
U.S. Appl. No. 10/837,186, filed Apr. 30, 2004, Morrison et al.
U.S. Appl. No. 10/837,059, filed Apr. 30, 2004, Logue et al.
U.S. Appl. No. 10/683,944, filed Oct. 1, 2003, Young.
Microelectronics Group, Lucent Technologies, Inc., Preliminary Data Sheet, May 1998, ORCA OR3Cxx (5 V), and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays, pp. 3, 69-80, available from Microelectronics Group, Lucent Technologies, Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103.
“Actel ES Family Digital Phase Lock Loop Usage”, by Joel Landry, Sep. 17, 1996, pp. 1-5, available from Actel Corp., 955 East Arques Avenue, Sunnyvale, California 94086.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; pp. 49-58 and 180-201, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
U.S. Appl. No. 09/684,529, filed Oct. 6, 2000, Logue et al.
U.S. Appl. No. 09/684,540, filed Oct. 6, 2000, Young et al.

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