Digital clock frequency multiplication circuit and method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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327119, 327120, H03B 1900

Patent

active

059330350

ABSTRACT:
A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

REFERENCES:
patent: 4654851 (1987-03-01), Busby
patent: 5216301 (1993-06-01), Gleeson, III et al.
patent: 5321734 (1994-06-01), Ogata
patent: 5389830 (1995-02-01), Buckingham et al.
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5530387 (1996-06-01), Kim
patent: 5548235 (1996-08-01), Marbot

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