Digital clock buffer circuit providing controllable delay

Details Digital clock buffer circuit providing controllable delay Digital clock buffer circuit providing controllable delay

1990-03-05

1992-06-02

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307603, 307606, 307595, 307597, 328 55, 328 66, 328155, H03K 5159, H03K 513

Patent

active

051189755

ABSTRACT:
A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

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