Digital circuit unit testing system utilizing signature analysis

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324 73R, 371 26, G06F 1100, G01R 3128

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active

045035369

ABSTRACT:
A system for testing digital circuit units at the design speed of the circuit. A first memory stores a minimized set of optimum generated predetermined test patterns for application to a unit under test. A second memory stores expected signature patterns corresponding to signature patterns that are derived from the unit under test in response to the predetermined test patterns when the unit under test is functioning properly. A signature analyzer derives signature patterns from a unit under test in response to the application of the test patterns to the unit. A comparator compares the derived signature patterns with the expected signature patterns and provides an indication of the results of the comparison. A clock provides a clock signal having a pulse rate that corresponds to the design speed of the unit under test; and a sequential counter responds to said clock signal by providing a sequential count to the first memory for addressing the first memory at storage positions therein having addresses corresponding to the sequential count to cause the predetermined test patterns to be read from the first memory and applied to the unit at a speed that corresponds to the design speed of the unit under test. The testing system further includes a backtracing system for enabling determination of the location of faults in the unit under test.

REFERENCES:
patent: 3082374 (1963-03-01), Buuck
patent: 3302109 (1967-01-01), Jones
patent: 3573751 (1971-04-01), DeLisle
patent: 3651315 (1972-03-01), Collins
patent: 3659087 (1972-04-01), Green et al.
patent: 3777129 (1973-12-01), Mehia
patent: 3787669 (1974-01-01), Muehldorf
patent: 4066882 (1978-01-01), Esposito
patent: 4168527 (1979-09-01), Winkler
patent: 4189778 (1980-02-01), Vogel
patent: 4192451 (1980-03-01), Swerling et al.
patent: 4216374 (1980-08-01), Lam et al.
patent: 4224690 (1980-09-01), Rockwell
patent: 4255792 (1981-03-01), Das
patent: 4271472 (1981-06-01), Saunders et al.
patent: 4277831 (1981-07-01), Saunders et al.
patent: 4441074 (1984-04-01), Bockett-Pugh et al.
Whitley, Testing System for Manufactured Circuit Cards, IBM Technical Disclosure Bulletin, vol. 22, No. 6, p. 2221, 11/79.
Rossero, Module Test With Computer Simulator and Random Pattern Generator, IBM Technical Disclosure Bulletin, vol. 25, No. 5, p. 2385, 10/82.
Palmquest, Logic Analyzer Delivers Test Patterns Too, Electronics, vol. 54, No. 18, p. 113, Sep. 8, 1981.
Sand, "Diode Matrix Replacement by Programmable Read Only Memories for Image Analyzer Control", Microscope, vol. 25, No. 1, (1977), pp. 47-53.

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