Digital circuit test generator

Details Digital circuit test generator Digital circuit test generator

1997-02-19

1998-11-03

Beausoliel, Jr., Robert W.

Excavating

364578, G06F 1100

Patent

active

058319964

ABSTRACT:
Automatic test pattern generator for generating test patterns that are capable of detecting faults in a digital combinational circuit comprises a first forward network capable of emulating the digital combinational circuit; a second forward network capable of emulating the digital combinational circuit in the presence of any one target fault from a specified set of faults, and receiving a set of control signals for selecting the target fault; a first backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the first backward network generating one fault activation objective corresponding to the selected target fault, and receiving first signal values computed in the first forward network for propagating the fault activation objective towards a primary output; a second backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the second backward network receiving second signal values computed in the second forward network for propagating the fault activation objective towards a primary output, both the first and second backward networks independently generating and propagating fault-effect propagation objectives towards one or more of its respective primary outputs; a first control device for generating the set of control signals corresponding to a target fault, and selecting the target fault one at a time from the specified set of target faults; means for merging one or more objectives propagated to the primary outputs of the first and second backward network; comparator device for comparing the first and second sets of primary output signals from each the first and second forward network in response to primary input signals, and determining whether at least one pair of corresponding primary outputs have different binary values and providing an output therefor; and, second control device for receiving the merged objectives from the backward network and the comparator output, and determining therefrom primary input values of the first and second forward network for detecting the target fault in the combinational digital circuit.

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