Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2001-10-11
2003-11-04
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C141S144000
Reexamination Certificate
active
06642766
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for suppressing erroneous operation resulting from noise superposed on a clock signal in an LSI.
Recently, in LSIs for use in processing audio signals, digital signal processors (DSPs) perform complicated operation processing and thus are required to operate at high-frequency clock speeds. At the same time, an output from an LSI has to be a signal synchronized with a clock signal that is a multiple of the sampling rate of the LSI. Also, for processors such as many which process both sound and video, a clock signal for use in operation processing and another clock signal for use in outputting an audio signal are totally asynchronous in many cases.
FIG. 6
is a circuit diagram of a known digital circuit, which is used in the LSI. In
FIG. 6
, a frequency divider
20
consists of a flip-flop
21
which operates synchronously with a signal output clock signal CK
1
and an inverter
22
. The frequency divider
20
divides the frequency of the signal output clock signal CK
1
and outputs the signal thus obtained as a signal S
1
. The low-potential-level (which will be herein referred to as an “L-level”) interval of the signal S
1
corresponds to one cycle of the clock signal CK
1
. The high-potential-level (which will be herein referred to as an “H-level”) interval of the signal S
1
is equal to an integral multiple of one cycle of the clock signal CK
1
.
A differentiator
30
consists of flip-flops
31
and
32
, which operate synchronously with an operation-processing-dedicated clock signal CK
2
, an inverter
33
and an OR gate
34
. The differentiator
30
generates a signal S
2
from the signal S
1
and outputs the signal S
2
. The signal S
2
falls in response to the trailing edge of the signal S
1
, and the L-level interval thereof corresponds to one cycle of the clock signal CK
2
.
A first counter
41
operates synchronously with the clock signal CK
1
, and counts the number of pulses of the clock signal CK
1
only when the input signal S
1
is in the L-level interval. A second counter
42
operates synchronously with the clock signal CK
2
, and counts the number of pulses of the clock signal CK
2
only when the input signal S
2
is in the L-level interval. The output CT
1
of the first counter
41
is used for, for example, generating a timing control signal supplied to a circuit in a succeeding stage of the LSI. The output CT
2
of the second counter
42
is used for, for example, signal generation timing control inside of the LSI.
In the known digital circuit, however, when noise is superposed on a signal output clock signal, noise components cause a large difference in operating speed between a circuit section which operates synchronously with the operation-processing-dedicated clock signal and another circuit section which operates synchronously with the signal output clock signal. Erroneous operation due to this difference might cause inconveniences in outputting.
FIG. 7
is a timing diagram illustrating the operation of the digital circuit shown in FIG.
6
and illustrates a situation in which noise is superposed on the clock signal CK
1
. As shown in
FIG. 7
, when noise with a higher frequency than that of the output clock signal CK
1
is superposed on the clock signal CK
1
, noise components also appear on the signal S
1
which is generated by dividing the clock signal CK
1
. As a result, in response to the noise components, the count CT
1
of the first counter
41
increases much faster than intended. In contrast, the signal S
2
via the differentiator
30
leaves only part of noise components. Thus, the second counter
42
, which operates in response to the signal S
2
, is not affected by the noise. As a result, a large difference in operation speed occurs between the count CT
1
of the first counter
41
and the count CT
2
of the second counter
42
. This difference affects timing control of the LSI and its peripheral circuits, and sometimes causes noise on a reproduced audio signal or erroneous operation of devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a digital circuit and a method for removing noise and whereby problems in LSIs, such as erroneous operation, can be obviated even when the noise is superposed on a clock signal.
Specifically, a digital circuit according to the present invention includes a clock generator for receiving a first clock signal and generates a raw clock signal synchronized with the first clock signal, a first circuit section which outputs the raw clock signal synchronously with a second clock signal, and a second circuit section which outputs, as a reproduced clock signal, the output signal from the first circuit section synchronously with the first clock signal.
In the inventive digital circuit, the raw clock signal synchronized with the first clock signal is synchronized with the second clock signal and output by the first circuit section. Then, the output signal from the first circuit section is synchronized with the first clock and output as a reproduced clock signal by the second circuit section. Accordingly, even when noise is superposed on the first clock signal, noise components of the reproduced clock signal are greatly reduced.
In the inventive digital circuit, the first clock signal is preferably a signal for outputting a particular signal and the second clock signal is preferably a signal for use in operation processing.
In the inventive digital circuit, the first circuit section preferably includes a flip-flop which receives the raw clock signal at a data input and receives the second clock signal at a clock input. Also, the second circuit section preferably includes a flip-flop which receives the output signal from the first circuit section at a data input and receives the first clock signal at a clock input.
In the inventive digital circuit, the frequency of the second clock signal is preferably higher than twice the frequency of the raw clock signal.
An LSI according to the present invention includes the digital circuit and a DSP which performs operation processing in response to the second clock signal.
Also, an inventive method for removing noise includes the steps of a) generating a raw clock signal synchronized with a first clock signal from the first clock signal, b) synchronizing the raw clock signal with a second clock signal, and c) synchronizing the signal obtained by the step b) with the first clock signal, thereby generating a reproduced clock signal.
In the inventive method, the raw clock signal synchronized with the first clock signal is synchronized with the second clock signal and output. This output signal is further synchronized with the first clock signal again and output as a reproduced clock signal. Accordingly, even when noise is superposed on the first clock signal, noise components of the reproduced clock signal can be greatly reduced.
In the above inventive method, the first clock signal is preferably a signal for outputting a particular signal and the second clock signal is preferably a signal for use in operation processing.
REFERENCES:
patent: 4153814 (1979-05-01), Burgert
patent: 4622690 (1986-11-01), Smith et al.
patent: 4973860 (1990-11-01), Ludwig
patent: 5099141 (1992-03-01), Utsunomiya
patent: 5570307 (1996-10-01), Takahashi
Callahan Timothy P.
McDermott & Will & Emery
Nguyen Linh
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