Digital circuit for suppressing fast signal variations

Details Digital circuit for suppressing fast signal variations Digital circuit for suppressing fast signal variations

1987-07-09

1989-08-29

Harkcom, Gary V.

Boots, shoes, and leggings

3581941, 455603, G06F 1531, H04N 544

Patent

active

048624047

ABSTRACT:
A digital circuit which receives a serial input signal and which suppresses fast signal variations. The digital circuit includes an integrator circuit (1) which generates a multi-bit signal by integration of the serial input signal. The output signal of the integrator circuit is applied to an evaluation circuit (2) which generates a serial output signal which assumes a first state when the multi-bit signal exceeds a first threshold value and a second state when the multi-bit signal is below a second threshold value.

REFERENCES:
patent: 4156134 (1979-05-01), Minner
patent: 4231031 (1980-10-01), Crowther et al.
patent: 4245347 (1987-01-01), Hutton et al.
patent: 4352202 (1982-09-01), Carney
patent: 4517564 (1985-05-01), Mosishita et al.
patent: 4573135 (1986-02-01), Dieterich
patent: 4630290 (1986-12-01), Kage
patent: 4697098 (1987-09-01), Cloke

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