Digital circuit for generating output pulses synchronized in tim

Telegraphy – Systems – Printing

Patent

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Details

178 695R, 307269, 328155, H03K 117, H03B 304, H03K 513

Patent

active

039463230

ABSTRACT:
A digital phase locked loop circuit for use in synchronizing output timing pulses with the positive going zero-crossings of an input data signal by quantitizing the input analog data signal as digital information, storing the digital information at given times by timing pulses, pre-programming a counter with a count corresponding to the quantitized digital information stored, and advancing or lagging an updated timing pulse in accordance with the timed count of the program counter which count is synchronized with the zero-crossings of the input data signal, whereby the updated timing pulses move to synchronism with the zero-crossings of the input data signal.

REFERENCES:
patent: 2976517 (1961-03-01), Fuller et al.
patent: 3755748 (1973-08-01), Carlow et al.

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