Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Patent
1986-09-17
1987-09-22
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
377117, 377121, H03K 2348, H03K 2352
Patent
active
046960201
ABSTRACT:
The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.
REFERENCES:
patent: 4034302 (1977-07-01), May
patent: 4041403 (1977-08-01), Chiapparolhi
patent: 4390960 (1983-06-01), Yamashita et al.
Etablissement Public de Diffusion dit "Telediffusion de France"
Etat Francais represent par le Secretariat d'Etat aux Postes et
Heyman John S.
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