Digital circuit for differential receiver for direct sequence sp

Details Digital circuit for differential receiver for direct sequence sp Digital circuit for differential receiver for direct sequence sp

1996-11-12

1998-08-25

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375200, 375330, 375331, H04K 100

Patent

active

057990352

ABSTRACT:
The circuit has two parallel channels for the processing of two components in phase (I) and in quadrature (Q). Each channel has filtering means (50(I)) and delay means (60(I)). The circuit also incorporates a multiplication circuit (70), an integration circuit (80) and a programming circuit (90). Several circuits of this type can be connected in cascade.

REFERENCES:
patent: 5202901 (1993-04-01), Chennakeshu et al.
patent: 5253268 (1993-10-01), Omura et al.
patent: 5311544 (1994-05-01), Park et al.
patent: 5528624 (1996-06-01), Kaku et al.
Patent Abstracts of Japan, vol. 95, No. 010, & JP-A-07 283762 (Fujitsu General Ltd.), 27 Oct. 1995.

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