Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-01-25
2002-01-08
Sircus, Brian (Department: 2839)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C333S012000, C174S250000
Reexamination Certificate
active
06337798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the design and fabrication of electronic equipment and, more particularly, to the design of a printed circuit board (PCB) that increases electromagnetic coupling between discrete decoupling capacitors mounted on the surface(s) of such PCB.
2. Description of the Related Art
A significant consideration in the design and fabrication of compact (and therefore densely assembled), high-speed digital equipment is the need to minimize the effects of ringing, crosstalk, radiated noise and other forms of electromagnetic interference (EMI). However, design approaches seeking to minimize EMI effects are generally susceptible to straight forward circuit analysis. In fact, although entire textbooks have been devoted to techniques for combating EMI, the subject continues to be viewed as “black magic”. See, for example, Howard Graham, “High-Speed Digital Design,” Prentice Hall PTR, Saddle River, N.J. (1993).
High-speed digital circuits and systems frequently draw large transient currents during short intervals, when, for example, logic circuits and devices change state. Often logic transitions take place with brief rise and fall times, under the control of increasingly high-frequency clock signals. Because realizable voltage sources for digital circuitry are characterized by series resistances and inductances, decoupling capacitors are commonly relied on to supply transient current requirements during transition intervals. The coupling capacitors are typically electrically connected between a voltage supply and ground and serve to mitigate the effects of the nonzero voltage supply source impedance. The decoupling capacitors therefore, tend to maintain the output of the voltage supply by providing a significant portion of the transient current.
However, the ability of commercially available capacitors to supply current at high frequencies is limited by the parasitic lead inductance that is characteristic of such capacitors. In addition to the inductance associated with capacitor leads, the finite inductance of each via that may be used, for example, to attach a power supply plane to a ground plane introduces a small, but measurable inductance. The magnitude of this inductance is approximately:
L
=
5.08
h
[
ln
(
4
h
d
)
+
1
]
where
L=inductance of via, nH,
h=length of via, inches
d=diameter of via, inches
Parasitic inductance is unavoidable because current flowing in a capacitor will create lines of flux. The effect of parasitic lead inductance is aggravated by the additional inductance that is inherent to the physical layout of electronic circuitry. This additional inductive component arises both from the conductive traces imparted to the PCB, as well as from the physical proximity of discrete components, both active and passive.
EMI may be encountered in PCBs in at least two modes. As suggested above, differential mode (DM) EMI results from currents that flow in a loop through various components or circuits on the PCB. DM EMI can be reduced either by reducing the current that flows in the loop, or by reducing the area subtended by the loop. EMI is also encountered as a result of voltage drops related to induced impedance. The form of EMI is referred to as common mode (CM) EMI because it may be transmitted across an entire circuit. CM EMI may be reduced by decreasing the rate of change of current (dI/dt) that causes the CM EMI, or by decreasing the inductance in the current path.
Decoupling capacitors are, as with any component of high-speed digital circuit, susceptible to both DM and CM EMI phenomena. A prevalent approach to reducing the effects of parasitic inductance associated with decoupling capacitors is simply to connect a number of decoupling capacitors in parallel between the voltage supply and GND. When the decoupling capacitors are connected in parallel, the effective parasitic inductance is reduced, approximately by a factor equal to the number of capacitors that are connected in the parallel configuration. It is not surprising, then, that a number of commercially available discrete capacitors, and capacitor arrays, are designed in this manner to minimize the parasitic inductance of capacitors. Specifically, AVX Corporation, Myrtle Beach, S.C., manufacturers and distributes a product line of capacitor configurations under various product designations, such as DCAP, Low Inductance Capacitor Array (LICA), the Power Plane Decoupling Capacitor, the Interdigital Capacitor and the Reverse Terminal Capacitor. Capacitor arrays such as the above and others are recognized as affording improved decoupling, with reduced parasitic inductance. However, such arrays typically command a price premium when compared to the standard surface mount technology (SMT) decoupling capacitor.
Accordingly, what is desired is an economical approach to the arrangement of multiple decoupling capacitors on a printed circuit board. The objective is to reduce parasitic inductance as well as EMI effects. Furthermore, it is another object of the invention to further reduce EMI by limiting the mutual inductance exhibited between capacitor bodies that are situated in proximity on a PCB. Reduction of mutual induction will also result in corresponding reductions in CM EMI. An additional desired result is the reduction in DM EMI by constraining the area of the current loop circumscribed by the decoupling capacitors. Finally, it is preferred that the above results be achieved with commonly available, discrete SMT decoupling capacitors, thereby avoiding premium prices that accompany exotic capacitor arrays.
SUMMARY OF THE INVENTION
The above and other objects, advantages and capabilities are achieved in one aspect of the invention by circuit assembly that comprises a printed circuit board (PCB) that is characterized by a first exterior surface, a first internal conductive layer, and a second internal conductive layer. First and second discrete capacitive elements, each having conductive terminals disposed at opposing extremities of the associated capacitive element, are laterally juxtaposed on the first exterior surface of the PCB so that the first conductive terminal of the first capacitive element is disposed adjacent to the first conductive terminal of the second capacitive element and is disposed remotely from the second conductive terminal of the second capacitive element. A first conductor couples the first conductive terminal of the first capacitive element to the first internal conductive layer; a second conductor couples the second conductive terminal of the first capacitive element to the second internal conductive layer; a third conductor couples the first conductive terminal of the second capacitive element to the second conductive layer; and a fourth conductor couples the second conductive terminal of the second capacitive element to the first internal conductive layer.
Another aspect of the invention contemplates a printed circuit board (PCB) characterized by a first exterior surface, a first internal conductive layer, and a second internal conductive layer. First and second discrete capacitive elements, each having conductive terminals disposed at opposing extremities of the associated capacitive element, are mutually juxtaposed on the first exterior surface of the PCB so that the first conductive terminal of the first capacitive element is disposed adjacent to the first conductive terminal of the second capacitive element and remotely from the second conductive terminal of the second capacitive element. A conductor array couples two of the conductive terminals to the first internal conductive layer and couples two of the conductive terminals to the second internal conductive layer.
Another additional manifestation of the invention is represented by a circuit assembly that comprises a printed circuit board (PCB) characterized by a first exterior surface, a second exterior surface, a first internal conductive layer, and a second internal conductive layer. First and second discre
Hailey Jeffrey C.
Steigerwald Todd W.
Dell USA L.P.
Prasad Chandrika
Sircus Brian
Skjerven Morrill & MacPherson LLP
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