Digital circuit arrangement detecting synchronizing pulses

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358155, H04N 508

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active

050538691

ABSTRACT:
In a digital circuit for detecting horizontal or vertical synchronizing pulses in a digital video signal, the video signal is applied to a level detector which supplies an extreme value signal which indicates the level of the synchronizing pulse at the end of a time interval. The extreme value signal represents the extreme value of the signal which has hitherto occurred in a time interval equal the time between two consecutive synchronizing pulses. In each period between two consecutive synchronizing pulses a new time interval is started at a predetermined instant outside the blanking interval. In order to generate a comparison signal, the extreme value signal is continuously reduced by a predetermined amount. The comparison signal and the digital video signal delayed by several sample clock periods are applied to a comparator which supplies a synchronizing signal during those periods when amplitude level of the delayed digital video signal is higher than the level of the comparison signal.

REFERENCES:
patent: 4698679 (1987-10-01), Balaban et al.
patent: 4707740 (1987-11-01), Stratton
patent: 4858008 (1989-08-01), Sieben
patent: 4860100 (1989-08-01), Rakhodai et al.
patent: 4963969 (1990-10-01), Kitaura et al.

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