Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-03-14
2008-10-21
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07440991
ABSTRACT:
Disclosed is a digital circuit which comprises input signals A[n−1:0], SH[log2n−1:0], and DAT[n−1:0], a barrel shifter for outputting data B[n−1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUM0when carry inputs are high and addition results SUM1when the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUM0or a SUM1computed for each of the groups according to each carry output by the carry computation circuit.
REFERENCES:
patent: 5508952 (1996-04-01), Kantabutra
patent: 2003/0145033 (2003-07-01), Bradley et al.
patent: 2004/0073593 (2004-04-01), Wen
patent: 2004/0167957 (2004-08-01), Choi
patent: 2004/0267862 (2004-12-01), Rarick
patent: 2000-163251 (2000-06-01), None
Minamitani Junichiro
Sasaki Tsuneki
Malzahn David H
McGinn IP Law Group PLLC
NEC Electronics Corporation
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