Digital channelizer having efficient architecture for...

Details Digital channelizer having efficient architecture for... Digital channelizer having efficient architecture for...

1999-02-26

2002-02-26

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06351759

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Reference is made to the following patent applications which are filed on even date herewith and which are incorporated herein by reference in their entirety:
(1) U.S. application Ser. No 09/259,031, filed Feb. 26, 1999, entitled “Digital Channelizer Having Efficient Architecture For Window Presum Operation and Method of Operation Thereof”;
(2) U.S. application Ser. No. 09/258,847, filed Feb. 26, 1999, entitled “Digital Channelizer Having Efficient Architecture For Cyclic Shifting and Method of Operation Thereof”;
(3) U.S. application Ser. No. 09/259,030, filed Feb. 26, 1999, entitled “Digital Channelizer Having Efficient Architecture For Window Presum Using Distributed Arithmetic for Providing Window Presum Calculations in One Clock Cycle”;
(4) U.S. application Ser. No. 09/259,029, filed Feb. 26, 1999, entitled “Efficient Digital Channelizer System and Method of Operation Thereof”; and
(5) U.S. application Ser. No. 09/259,127, filed Feb. 26, 1999, entitled “Digital Channelizer Having Efficient Architecture For Presum Discrete Fourier Transformation Selectively of Real or Complex Data and Method of Operation Thereof”.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to filters for dividing an input bandwidth into a plurality of channels and more particularly, to a digital channelizer for satellite communication applications using discrete Fourier transformation (DFT) to divide the input bandwidth into channels.
2. Description of the Prior Art
Digital channelizers in satellite communication systems have several design constraints. High computation complexity is required which requires highly complex integrated circuit logic function and interconnections. High power consumption by integrated circuits can lead to high operating temperatures which could contribute to channelizer malfunction or failure. The system clock rate is required to be sufficiently high to support a high data throughput but should be as low as possible to lessen power consumption which contributes to the aforementioned possible high operating temperatures. The power consumption of a digital channelizer is proportional to the clock rate and the type of integrated circuits which implement the required high computational complexity. Furthermore, excess hardware can interfere with processing efficiency and be a source of potential malfunction.
FIG. 1
illustrates a block diagram of a prior art digital channelizer
10
which functions as a down converter and filter which divides a wideband input bandwidth into a plurality of equally spaced channels. The channelizer
10
is representative of channelizers using DFT which have been described in the literature. See Multirate Digital Signal Processing, published in 1983 by Prentice Hall, Englewood Cliffs, N.J., written by Crochiere and Rabiner, which publication is incorporated herein by reference in its entirety. Such systems have applications in wideband satellite communication systems.
The INPUT signal is applied to a bandpass filter
12
which passes a selected wide bandwidth for division into N equally spaced channels each of a narrower bandwidth. For example, a wideband signal of 320 MHz. may be passed by the bandpass filter
12
for division into sixteen 20 MHz. wide channels. The bandpass filtered signal is applied to analog to digital converter
14
which samples the bandpass filtered signal. A representative frequency spectrum resultant from sampling is described further below in conjunction with
FIGS. 3A and 3B
. Each sample is comprised of a multiple bit word. A serial stream of multiple bit words is outputted by the analog to digital converter
14
as an input to demultiplexer
16
which produces D outputs
18
. The variable D may equal the variable M known as the decimation rate. The demultiplexer
16
functions as a multiple tapped delay line with each parallel output being outputted from a different tap of the delay line. The D outputs
18
of the demultiplexer are applied to window presum computer
20
. The window presum computer
20
functions in a well-known manner to process the sequence of words within a window of L words by multiplying each corresponding word in a plurality of equal subparts R of the window containing N words by a window presum function coefficient and summing the resultant multiplication products to produce the sum of the multiplication products where R=L/N. The individual summed multiplication products, after further processing including DFT as described below, are outputted as individual ones of the N channels. The number of outputted channels may be selected to be less than N.
For example, a sequence of ninety-six words, outputted by the demultiplexer
16
, is broken up into four subparts each containing twenty-four words. Each of R corresponding words, e.g. words
0
,
24
,
48
and
72
, from a different subpart, are multiplied by their preassigned window presum function coefficient and summed to produce an output summation which is subsequently processed into one of the N output channels. The window presum computer
20
has D inputs and N outputs. The relationship between M, D and N, which is the DFT size and the number of possible channels, affects the architecture of the window presum computer
20
. Words stored in a number of registers (not illustrated), e.g. words
0
,
24
,
48
and
72
, equal to the R subparts in the window processed by the window presum computer
20
, are summed after multiplication by their preassigned window presum function coefficient to produce the output summation.
The window presum computer
20
has been implemented by the Assignee with parallel data processing paths using integrated circuits with M not being equal to N. The number of processing paths I used by the Assignee to perform parallel data processing satisfies the relationship I equals the greatest common divisor of N and M which is expressed hereafter as GCD(N,M).
The N outputs from the window presum computer
20
are applied to a cyclic shift
24
, which provides phase adjustment, for processing into each channel by DFT. The phase produced by the cyclic shift
24
is applied to the resultant N word outputs from the window presum computer by a calculated number of shifts. The operation of cyclic shifting is well known and is, for example, described in the aforementioned publication on pp. 320-323. The number of shifts of the output words of the window presum computer
20
by the cyclic shift
24
is determined by computing the value of the relationship mM*modulo N or −mM*modulo N. The variable m is an output index variable which ranges from zero upward to positive integers. The output from the cyclic shift
24
, which has N channels, is applied to a discrete Fourier transform apparatus
26
having N inputs which transforms the output from the cyclic shift
24
into the N output channels.
FIG. 2
illustrates a conceptual block diagram of the window presum algorithm which represents the window presum processing performed by the system of FIG.
1
. The sampled output of L individual words is shifted into a shift register which stores the sequential words outputted by the analog to digital converter
14
. The input data are shifted into the shift register, which has a number of subparts R, e.g. 4 in the above example. The number of words per subpart (the DFT size) is equal to the number N of output channels. The shift register has an analysis window L words long which is R times the size N of the discrete Fourier transform. The sum of the individual R subparts contains the words which are further processed to individual channels by DFT. The data in the shift register are weighed with a time reverse window according to equation 7.70 on page 317 of the aforementioned publication to produce a windowed sequence as illustrated. The sequence is processed as blocks of samples starting at r=0 which are time aliased. The resultant summation is processed by a cyclic shift
24
through a number of shifts equal to mM*modulo N or −mm*modulo N and i

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