Digital camera shutter control circuit having memory read-out/sh

Details Digital camera shutter control circuit having memory read-out/sh Digital camera shutter control circuit having memory read-out/sh

1976-06-30

1980-03-04

Adams, Russell E.

354 50, 354 60A, 354 51, G03B 708

Patent

active

041914597

ABSTRACT:
A camera shutter digital control circuit having a counter for counting a number of pulses representative of exposure time and for reading-out the counted pulses to control exposure time. An adjustable delay circuit synchronizes shutter opening and the initiation of memory read-out. Upon the initiation of shutter opening a signal is applied to the delay circuit, which is adjusted to develop a delay equal to a particular shutter opening time. The delayed signal is then applied to initiate reading-out of the control pulses so that the exposure time is controlled in synchronism with the shutter opening.

REFERENCES:
patent: 3742826 (1973-07-01), Kohtani
patent: 3748979 (1973-07-01), Wada
patent: 3824608 (1974-07-01), Toyoda
patent: 3836262 (1974-09-01), Yata et al.
patent: 3843265 (1974-10-01), Egli et al.

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