Digital calibration techniques for segmented capacitor arrays

Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source

Reexamination Certificate

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C331S00100A, C331S03600C, C331S044000, C331S179000

Reexamination Certificate

active

07812678

ABSTRACT:
An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a calibration number of the fine capacitors having a combined capacitance that most closely matches a capacitance of one of the coarse capacitors.

REFERENCES:
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patent: 2003/0133522 (2003-07-01), Staszewski et al.
A. V. Rylyakov et al., “A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI,” 2007 IEEE International Solid-State Circuits Conference / Session 9 / Clocking / 9.1, Feb. 13, 2007, pp. 172-173.
Robert Bogdan Staszewski et al., “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004, pp. 2278-2291.
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