Digital bypassable register interface

Details Digital bypassable register interface Digital bypassable register interface

1977-02-22

1978-08-29

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 71, 328 72, 307DIG1, H03K 1702

Patent

active

041106970

ABSTRACT:
An interface for transmitting data in either a clock edge triggered synchous transmission mode or an asynchronous transmission mode. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting the bypass path to an output means or to provide synchronous transmission by connecting the output of the edge triggered register to the output means.

REFERENCES:
patent: 2866092 (1958-12-01), Raynsford
patent: 3461313 (1969-08-01), Hansen
patent: 3693028 (1972-09-01), Fussell
patent: 3742466 (1973-06-01), Hamm et al.
patent: 3829786 (1974-08-01), Hoffman et al.

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