Digital BIST test scheme for ADC/DAC circuits

Details Digital BIST test scheme for ADC/DAC circuits Digital BIST test scheme for ADC/DAC circuits

2007-09-18

2007-09-18

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C324S763010

Reexamination Certificate

active

11350227

ABSTRACT:
A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

REFERENCES:
patent: 5583502 (1996-12-01), Takeuchi et al.
patent: 5617037 (1997-04-01), Matsumoto
patent: 5818370 (1998-10-01), Sooch et al.
patent: 2003/0179118 (2003-09-01), Mizutani et al.

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