Digital binary increment circuit apparatus

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G06F 750

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active

044173164

ABSTRACT:
A circuit is illustrated for performing an increment function wherein a savings of parts is obtained by using an inverter for two different functions thereby decreasing land area required for implementing the integrated circuit on a chip.

REFERENCES:
patent: 3989940 (1976-11-01), Kihara
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4054788 (1977-10-01), Maitland et al.
patent: 4153939 (1979-05-01), Kudov
patent: 4218750 (1980-08-01), Carter et al.
patent: 4280190 (1981-07-01), Smith
Elliott, "Increment-Decrement Logic", IBM Tech. Disclosure Bulletin, vol. 11, No. 3, Aug. 1968, pp. 297-298.

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