Digital binary array multipliers using inverting full adders

Details Digital binary array multipliers using inverting full adders Digital binary array multipliers using inverting full adders

1986-11-14

1988-08-30

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

047681616

ABSTRACT:
Digital binary multipliers are provided which include first and second inverting full adders, each having first, second and third input terminals and first and second output terminals, the first output terminal of the first adder being connected to the first input terminal of the second adder with the first, second and third input terminals and the first and second output terminals of the second adder having a relationship with respect to the input and output terminals of the first adder such that corresponding input and output terminals have opposite signal polarities or complementary terminals, i.e., when one of these input or output terminals of the first adder has a true polarity signal, its corresponding input or output terminal of the second adder has a complemented polarity signal.

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"A GaAs 16.times.16 Bit Parallel Multiplier" by Y. Nakayama in IEEE Journal of Solid State Circuits, vol. SC-18, No. 15, Oct. 1983, pp. 599-603.
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