Digital banking circuit

Details Digital banking circuit Digital banking circuit

2005-11-01

2005-11-01

Phu, Phuong (Department: 2631)

Pulse or digital communications

Receivers

Interference or noise reduction

C455S223000

Reexamination Certificate

active

06961396

ABSTRACT:
A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval. An “adaptive” blanking circuit is also described in which the blanking interval is terminated when the transition which triggered the start of the blanking interval propagates through an entire signal path, such that the blanking interval is automatically adjusted to be the same as the signal path delay.

REFERENCES:
patent: 4521917 (1985-06-01), Holt, Jr.
patent: 5418410 (1995-05-01), Tisinger
patent: 5463662 (1995-10-01), Sutterlin et al.
patent: 5801651 (1998-09-01), Nehoda

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