Digital audio data receiver without synchronized clock...

Details Digital audio data receiver without synchronized clock... Digital audio data receiver without synchronized clock...

1998-11-16

2004-08-03

Nguyen, Duc (Department: 2643)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Digital audio data processing system

C375S355000

Reexamination Certificate

active

06772021

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to digital audio interfaces, and in particular to receivers which can receiver S/PDIF and AES digital audio signals.
S/PDIF is a digital audio interface standard commonly used in consumer digital audio equipment, including personal computers. AES is a digital audio interface which is prevalent in professional equipment. Both of these formats are a one direction serial interface which is Manchester encoded in order to provide an embedded clock so that a single data wire is sufficient for the interface.
Manchester encoding encodes digital bits serially in the following manner. The data is sent in a number of bit cells, with each cell having either a one or a zero. It is mandatory that there be a signal transition from low to high or high to low at the boundary of each cell. A one is encoded by having a transition in the middle of the cell, while a zero is encoded by having no transition in the middle of the cell. This is illustrated in
FIG. 1
, which shows a number of cell boundaries
10
. As can be seen, the zeros have no transitions in the middle of the cell, while the ones do. Note that the zero can be either be a high or low value within a cell, and that the one can either start out low or start out high, ending the opposite. A preamble is indicated by violating the Manchester rule of having a transition at the cell boundary. Thus, a preamble is typically one and one-half bit cells long, and can be detected since there is no transition at the bit cell boundary.
In audio equipment, the original audio data from a human voice, musical instrument, etc., is in analog form. This is sampled at a high data rate, with each sample being then converted into a multi-bit digital value. These digital values can then be sent serially from one place to another in the digital circuit or to other digital equipment using Manchester coding.
To receive a Manchester coded signal, a receiver will typically extract the embedded clock using a phased locked loop (PLL). A phased locked loop is a combination of digital and analog circuitry which allows the generation of a clock corresponding to the bit cell transitions of the Manchester encoded data. Using the recovered clock, the data can then be covered. As can be seen, once the clock is obtained and the transition boundaries are then known, the recovering circuit can simply look to see whether or not there is a transition near the middle of the clock.
Where a particular piece of audio equipment receives multiple digital audio streams, one method is to transmit a “house sync” and require all devices sending data to become phase locked to the house sync. In this manner, the receiver would not require a PLL. A disadvantage to this approach is that the house sync needs to be communicated to all transmitting devices, and most consumer equipment such as CD-players, CD-ROMs, DAT players and Mini-disks do not provide the sync-lock feature this would require.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for receiving digital audio data which does not require the recovery of a clock from the data. Instead, the digital audio data is sampled at a rate greater than a clock rate of the digital audio data. Appropriate transitions in the digital audio data are detected to allow reconstruction of digital values represented by the digital audio data.
The unique application of a type of sampling technique to digital audio data eliminates the need for a PLL, and allows recovery of the audio data with simple circuitry. No analog circuitry is required, and the device can be constructed purely digital (CMOS) circuits. The invention allows the system clock for the circuit to be generated by a typical crystal oscillator. This makes it easy to have a high quality (low phase noise) system clock. Another advantage is that multiple, independent data input streams can be received using a single system clock. There is no need for a “house sync”, since the circuit easily recovers the data using the system clock, without recovering the digital audio clock. This enables multiple independent data streams at widely-different clock rates to be received.
In a preferred embodiment, the invention doesn't even use the transition in the middle of the bit cell to detect the data. Rather, this mid-cell transition for an encoded one is ignored. Instead, the invention relies on the recognition that the bit-cell boundary transitions will always be in the same direction for a digital one and in opposite directions for digital zero. Thus, by comparing a bit cell boundary transition to the last bit cell boundary transition (which has been saved), the value of the digital bit can be determined.
Preferably, the bit stream is decoded using a state machine. Digital counters are used to determine the pulse width between transitions. By detecting a preamble, and setting a “sync size ” value in a register, a stored reference which is 1.5 times that of a zero is provided. By ignoring transitions which are less than two-thirds of the sync size, the bit cell transitions can be enabled for detection and used to decode the data.
For a further understanding of the nature and advantages, of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.


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patent: 5600682 (1997-02-01), Lee
patent: 6097322 (2000-08-01), Tournier
patent: 6449519 (2002-09-01), Kuwaoka

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